真乄科技業的頂尖投資團隊

Note: this is the first part of the whole article. Second part will be released next week. Stay tuned!
The semiconductor industry is currently sailing through unstable and largely uncharted waters, in search of new applications and supporting technologies that can propel further growth. Smartphones, still the leading semiconductor application, are on the road of maturity, heading towards lower growth rates of ~6% by 2020. Furthermore, front-end device scaling is becoming more complex and deviates from the cost reduction path it followed in the previous decades, according to Moore’s law.

As the semiconductor industry undergoes transformation, the spotlight turns to advanced packaging, as a key rejuvenation enabler. Advanced packages are sought as a solution for further cost cutting along the performance roadmap and as a technology addressing future applications with package level system integration, what can be referred to as the functional roadmap.
As package segmentation for various IoT scenarios is under way, along with rising interest in the automotive segment and wearables, a plethora of package architectures are being proposed. This is particularly true with respect to substrate technology in the competitive sub 15/15 um line width space landscape. Proposed substrate architectures vary from advanced FC CSP/BGA, coreless substrates, FO WLP solutions and 2.5D/3D with a clear trend toward multi die System-in-Packages (SiP). Innovative packaging companies in this landscape are no longer just OSATs, but also foundries and IDMs.
These future packaging technologies are exciting as they are complex, which is why Yole Développement has a dedicated task force assigned to the areas of advanced substrates and SiP. Our lead analysts for the areas of advanced substrates and SiP, Andrej Ivankovic (ivankovic@yole.fr) and Jerome Azemar (azemar@yole.fr), sat down with STATS ChipPAC VP of WW Product Technology Marketing, Dr. Scott Sikorski and Director of Market Intelligence, Boris Petrov, respectively, to discuss the development of advanced packaging and STATS ChipPAC’s specific position. STATS ChipPAC is an assembly and test house on the leading edge of packaging technology, an early FO WLP technology adopter and solution provider, now ready with a complete single die to SiP portfolio to address future applications.

(Source: Status of the Advanced Packaging Industry 2015, Yole Développement)

Yole Développement: STATS ChipPAC has been on the forefront of assembly and packaging technology for two decades and has recently undergone structural changes, now operating under the hat of the JCET group. Can you please introduce STATS ChipPAC and its current activities?

STATS ChipPAC: STATS ChipPAC continues to pursue the same mission as before the acquisition by JCET Group. We are fundamentally focused on servicing the semiconductor industry with innovative integration solutions, utilizing a range of packaging technologies including wirebond, flip chip, wafer level and System-in-Package (SiP). As the primary industry Fan-out Wafer Level Packaging (FOWLP) innovator, we continue to develop our eWLB platform and rapidly expand capacity which has been in strong demand over the past several quarters. We continue to offer a comprehensive set of flip chip solutions for mobile, networking, computing and consumer electronics. Our next major business expansion will revolve around SiP to support growing customer demand. Our manufacturing operations are in Singapore, South Korea, and China with a long term service agreement with Winstek Semiconductor, our former subsidiary located in Taiwan.

YD: The combination of JCET and STATS ChipPAC technology on first glance represents a significant enlargement of the JCET group packaging portfolio, now ranging from discretes and leadframes to advanced packages. Can you please explain in more detail what effect JCET group has on the portfolio and future development of STATS ChipPAC?

SCP: Yes, the combination was very attractive because of the incredible synergy between the two companies in regards to technology portfolio as well as customer footprint. JCET has extremely solid credentials in wirebond packaging, servicing a much broader range of applications than STATS ChipPAC was focused on, while we clearly bring a very strong portfolio of advanced technologies. The JCET Group is now able to address a much broader total available market (TAM) than either company could alone. We are already seeing benefits of cross-selling services to our customers. We expect these efforts, coupled with our strong traction in eWLB and SiP, to result in higher than industry average growth for the next several years. STATS ChipPAC will remain the FOWLP and SIP center of competency for the JCET Group and all laminate based flip chip activities are being consolidated into our factories.

YD: The semiconductor industry is going through a turbulent era. The mobile sector is still the main driver of semiconductor growth but is slowing down causing a ripple effect of consolidation, in search of new markets and applications. Increasing semiconductor content in the automotive industry and the development of the Internet of Things (IoT) are some of the most frequently mentioned solutions for growth acceleration. In your opinion, what opportunities lie ahead that can turn the semiconductor industry from a situation of decline to rejuvenation? What is STATS ChipPAC doing to adapt to new circumstances and how are you preparing for potential new markets and applications?

SCP: Yes, the plateauing of mobile convergence device growth is indeed creating a pause in semiconductor industry growth as we’ve seen over the past 18 months or so, especially due to product mix changes towards low-end smartphones and overall price declines. Going forward, it appears that the industry can expect help from two key phenomena. First, the further electrification of vehicles and an increase in the amount of semiconductor content per automobile sold. The second is IoT, a very broad and somewhat inconsistently used term that includes many current products as well as a plethora of future applications.

Beyond automotive and IoT, it is clear that the trend toward the modularization of functionality to cost effectively and reliably package devices of disparate semiconductor technologies is a game changing trend. The miniaturization associated with this modularization puts the solution space squarely in the wheelhouse of the OSAT industry. You have seen all of the tier 1 OSAT players responding to this SiP phenomenon. While the OSAT growth projections may be anemic when you look at the “traditional” packaging market, by including SiP, the OSAT TAM growth rate is expected to be much higher than the overall semiconductor market and will offset the relative decline of OSAT revenue in the mobile segment.

YD: Could new opportunities in the Chinese market help grow semiconductor business? How are the needs of the Chinese market different than other established markets (US, Europe, rest of Asia)? Are there any other regions globally that might present an opportunity to the semiconductor industry?

SCP: Yes, absolutely! We see China as having the highest semiconductor growth rates of any region and this translates into increased OSAT opportunities. Historically, the Chinese market has required somewhat less complex technologies than some of the established markets, but we see this rapidly changing. As Chinese brands compete with their Japanese and Western counterparts, they need to provide equivalent packaging and test solutions. We now see Chinese customers driving advanced technology requirements that are similar to other developed geographies. The ability to provide advanced technology solutions in China has become very important since the Chinese customer base usually prefers local content.

Given that the JCET Group is the leading Chinese OSAT with the largest manufacturing footprint in China combined with STATS ChipPAC’s technology portfolio, we believe we are exceedingly well positioned to gain market share in this region. STATS ChipPAC is employing the very broad and deep relationships that JCET has with Chinese customers to promote our technology and this is going very well – better than expected.

YD: STATS ChipPAC is a pioneer in Fan-Out Wafer-Level-Packaging (FO WLP), in particular due to early promotion and manufacturing of the eWLB technology. Today, a variety of FO WLP technologies are emerging bringing more players to the market. FO WLP technology has been on a path of solid growth, but is expected to make a stronger push in the following years. Do you agree with that and could you explain what are the main market drivers impacting this growth? How is STATS ChipPAC involved today in the FO WLP landscape?

SCP: Yes, we would agree with you. FOWLP represents a very important market trend going forward. The fundamental advantage of FOWLP is that you eliminate the substrate and by doing that you (1) eliminate an interface which gives you enhanced reliability in many cases, (2) you reduce cost because the substrate is often the single most expensive part of the packaging cost, and (3) you reduce the thickness or height of the overall packaged device, critically important for mobile and other space constrained applications. In addition, you get better electrical performance due to shorter interconnections and lower inductances. The net result is an extremely compelling packaging solution for a wide range of applications.

STATS ChipPAC recognized these advantages very early on, investing significant resources and capital to develop the industry’s leading FOWLP technology under our flagship eWLB platform. We have been in high volume production for over 6 years now and have shipped 1 billion units to an increasingly diverse customer base. All of this is turnkey business, so it has positive implications on our test business as well.

YD: What are the main markets and applications driving Fan-Out WLP growth? What are their requirements?

SCP: eWLB has been exceptionally successful in mobile applications such as baseband processors, RF transceivers, codecs and power management ICs due to the premium placed on cost effectively achieving the smallest possible form factor with better electrical performance. eWLB applications such as PMIC and RF with 1 to 3 RDL designs provide a very competitive solution with respect to form factor, performance, and cost compared to flip chip laminate solutions.

While the smartphone segment was the early adopter, we now see increasing adoption in market segments such as automotive Advanced Driver Assistance Systems (ADAS), Internet of Things, wearable electronics, MEMS and sensors. Generally, if the end application requires a reduction in X-Y size, FOWLP can usually provide a superior solution in terms of cost and performance.

YD: What are the advantages of Fan-Out WLP for these applications versus other packaging platforms?

SCP: The advantages of eWLB stem from the basic fact that the technology allows you to eliminate one level of interconnection. In traditional wirebond and flip chip packaging, the structure has two main interconnections, chip-to-package and then package-to-PCB. eWLB allows for the elimination of the discrete chip-to-package interconnect (no flip chip bump or wirebond) which provides fundamental advantages in cost, reliability and performance. In this sense, eWLB is a revolutionary technology whereas the transition from wirebond to flip chip, which is just a change in the chip-package interconnection type, is more evolutionary.

With respect to the handset market, the major attractions are smaller form factor (both X-Y and thickness) and better electrical performance, enabling larger batteries and longer battery life. The fan-out structure allows a significant increase in routing density and the thin film process provides an unparalleled reduction in package size and thickness which is not attainable with substrate-based packages. The smaller form factor helps to free up space on the circuit board, creating the option for a larger battery to be used. The short interconnection lengths combined with thinner dielectric materials also produce better electrical performance with a significant reduction in power consumption, thereby improving battery life.

YD: Looking at technology level, several substrate types are being proposed and developed to tackle the sub 10/10 um L/S area. On one hand we have organic WLP substrates, chip first or chip last and with or without Cu pillars such as eWLB, Amkor SWIFT, Deca Technologies adaptive patterning, TSMC inFO or ASE Chip Last and on the other dual damascene type substrates, such as SPIL SLIT or Amkor SLIM. Could you explain to us the differences and targets of these technologies? How do they compete? What would be the main pros and cons between these approaches, in terms of technology, manufacturability and cost?

SCP: Dual damascene technologies offer L/S below 1/1um with higher density via design rules and, if proven viable, will be suitable for silicon (Si) partitioning and high bandwidth die-to-die connection, large dies / large package configurations. WLP technologies, either chip-first or chip-last, use RDL processes and are scalable down to 2/2um L/S. STATS ChipPAC’s eWLB technology is a chip-first, face down wafer level process with fewer manufacturing steps (no copper column bumping for example) and less indirect materials required, resulting in an inherently lower cost. With the ability to partition silicon and embed passive devices into a design, eWLB is a powerful integration technology for 2.5D and 3D PoP or SiP solutions. We’ve explored other approaches, weighing out the costs and benefits of each one. With the proven benefits and scalability of eWLB technology, we have found this to be the best approach for our customers’ requirements.

YD: What FO WLP solutions does STATS ChipPAC offer and what approaches do you plan to focus on in the future?

SCP: STATS ChipPAC is firmly committed to our industry leading eWLB technology as supported by our capacity expansion happening this year. We continue to develop advanced 2.5D and 3D FOWLP package designs while implementing further process optimizations, such as panel manufacturing, which will drive significantly better capital intensity and a lower unit cost for larger body sizes.

YD: Fan-In WLP (FI WLP) is already a mature platform, somewhat out of the limelight, but experiencing continuous innovation heading towards HVM die sizes larger than 9 mm x 9 mm and bump pitches lower than 0.4 mm. How do FI and FO WLP complement each other? Unmatchable form factor and cost are main advantages of FI WLP. Apart from distribution surface limited to die size, what are the limitations? How does the future of the FI WLP market look like, having in mind fast development and promotion of other emerging advanced packaging technologies?

SCP: FIWLP is constrained by the size of the die by definition, so in advanced node products where the die sizes tend to run smaller, it becomes difficult to get all of the I/O that you need for the application within the footprint of the die itself. This is where FOWLP helps out by allowing you to expand the body size to enable the required I/O while still maintaining a very a small form factor at a very attractive price point. We expect WLCSP to continue to have market success for the foreseeable future, driven largely by demand for 200mm applications in older Si nodes and the gradual migration from wirebond to WLP in smartphones and wearable electronics.

YD: STATS ChipPAC has a special approach to FI and FO WLP processing, a joint platform named FlexLine, characterized by combined FI and FO WLP manufacturing, independent of incoming wafer sizes. Can you please give more insight into the idea behind this platform and how it is different from other WLP approaches?

SCP: Yes, we have devised an innovative manufacturing method, called FlexLineTM, which evolved from our eWLB process. Unlike conventional WLP, the first step in the FlexLineTM process is to thin and singulate the incoming Si wafer. The individual die are then reconstituted into a uniform processing size, making the original wafer diameters irrelevant as this no longer dictates manufacturing capacity or limits process capabilities. Using the FlexLineTM method, 200mm wafers can be reconstituted into 300mm or larger carrier sizes, providing customers with greater potential for cost reduction. With unprecedented flexibility in producing both FOWLP and FIWLP on the same manufacturing line, we are able to achieve higher utilization rates and economies of scale.
The encapsulation process which is inherent to FlexLineTM also provides the option to apply a protective coating to the exposed Si surfaces of WLCSP for increased quality and reliability. The polymer sidewall structure of the encapsulated WLCSP (eWLCSP) all but eliminates mechanical damage such as chipping and cracking that commonly occurs in traditional WLP processing and provides a measureable increase in component strength.
Unique to the FlexLine is the ability to seamlessly transition from fan-in to fan-out package designs as a customer’s requirements change over time due to factors such as increased I/O density, die shrink, integration of different ICs, fine pitch board assembly, etc. We are currently running a healthy mix of both FIWLP and FOWLP on our FlexLineTM and this has helped keep the line completely loaded over the last year, giving us confidence for the additional investments needed to nearly double our FlexLineTM capacity this year.

YD: Every year, the applicability of panel based manufacturing to WLP, its feasibility and market readiness comes into question. Apart from the chip last coreless substrate approach, which falls more into the category of Flip Chip packages than WLP, all other developments in the sub 10/10 um L/S area are wafer level based. Having in mind that TSV based technologies are targeting the high end high pin count applications and are starting to ramp up and a number other wafer level based TSV less technologies are in development (advanced eWLB, adaptive patterning, SLIM, SWIFT, SLIT, inFO etc.), is there a need for panel level manufacturing? Furthermore, if we look at potential high volumes coming from IoT, most of the packaging technology is already available, with apparently no real need for panel processes. Perhaps, panel level manufacturing will end up as niche manufacturing for specific applications, rather than mainstream? Could you share your opinion on panel level manufacturing and explain which activities is STATS ChipPAC undertaking in this domain?

SCP: What we have found is that panel level processing is the most sensible for larger body sizes, say above 10x10mm. Below that size, the time and expense of reconstitution and singulation reduce the savings from doing RDL on such a large format. You need applications that require larger body sized product, and again, it is better if the application allows for a reduction in body size. If not, some of the more recent low cost substrate technologies like Embedded Trace Substrate (ETS) and Molded Interconnect System (MIS) are very competitive cost-wise and it becomes difficult to generate much savings against them with a panel approach at this time. I don’t know if I would call it “niche”, but like all other technologies, we expect it to have a “sweet spot” where it is most compelling.

YD: In parallel with WLP and TSV solutions, flip chip substrates (cored and coreless) are continuing their progress aiming to compete for advanced packaging applications, from mobile devices to servers. Package substrate technology comes from the PCB manufacturing infrastructure, used to somewhat coarser L/S and pitches. Nevertheless, fcB/LGA substrates are today standard for demanding high end applications – a variety of CPUs and GPUs - and coreless substrates are already in HVM in today’s smartphones. How far can advanced flip chip substrates go and what kind of competition are they to WLP and TSV based packages?

SCP: Both cored and coreless substrate technologies offer a path down to 8/8um with a possible extension to 5/5um with the former using ABF build up and latter using PPG build up processes. However, yield and substrate manufacturing processes are not yet mature in comparison to FOWLP technologies available today, which are scalable down to 2/2um L/S with more advanced via design rules than what is available in cored and coreless designs. More advanced Photo Imageable Dielectric (PID) and Photo-Imageable Organic Interposer (POI) technologies approach the design rules in both L/S and via density to those offered by FOWLP, however, their yield and maturity is far from HVM ready. In general for L/S below 8/8um, FOWLP is a competitive and more attractive solution compared to flip chip based packages since the panel processing method makes the assembly process less sensitive to warpage related issues and can extend the package body size up to 15x15mm and beyond.

Note: this is the second part of the whole article. First part is available here. The semiconductor industry is currently sailing through unstable and largely uncharted waters, in search of new applications and supporting technologies that can propel further growth. Smartphones, still the leading semiconductor application, are on the road of maturity, heading towards lower growth rates of ~6% by 2020. Furthermore, front-end device scaling is becoming more complex and deviates from the cost reduction path it followed in the previous decades, according to Moore’s law.

As the semiconductor industry undergoes transformation, the spotlight turns to advanced packaging, as a key rejuvenation enabler. Advanced packages are sought as a solution for further cost cutting along the performance roadmap and as a technology addressing future applications with package level system integration, what can be referred to as the functional roadmap.
As package segmentation for various IoT scenarios is under way, along with rising interest in the automotive segment and wearables, a plethora of package architectures are being proposed. This is particularly true with respect to substrate technology in the competitive sub 15/15 um line width space landscape. Proposed substrate architectures vary from advanced FC CSP/BGA, coreless substrates, FO WLP solutions and 2.5D/3D with a clear trend toward multi die System-in-Packages (SiP). Innovative packaging companies in this landscape are no longer just OSATs, but also foundries and IDMs.
These future packaging technologies are exciting as they are complex, which is why Yole Développement has a dedicated task force assigned to the areas of advanced substrates and SiP. Our lead analysts for the areas of advanced substrates and SiP, Andrej Ivankovic (ivankovic@yole.fr) and Jerome Azemar (azemar@yole.fr), sat down with STATS ChipPAC VP of WW Product Technology Marketing, Dr. Scott Sikorski and Director of Market Intelligence, Boris Petrov, respectively, to discuss the development of advanced packaging and STATS ChipPAC’s specific position. STATS ChipPAC is an assembly and test house on the leading edge of packaging technology, an early FO WLP technology adopter and solution provider, now ready with a complete single die to SiP portfolio to address future applications.

(Source: Status of the Advanced Packaging Industry 2015, Yole Développement)

Yole Développement: System-in-Packages (SiP) are a hot topic, both for high end and lower end applications, whether it’s 2.5D TSV, FO WLP SiP or Flip Chip cored/coreless packages. How do you see the SiP market potential and future evolution? What are the main drivers, bottlenecks and competition to SiP? How is STATS ChipPAC positioned to address the SiP market?

STATS ChipPAC: As I mentioned earlier, we see SiP as a new growth engine for the OSAT industry. Three major market drivers for SiP are (1) mobile devices (such as power amplifiers, digitial baseband, WLAN, GPS modules and Bluetooth®); (2) organic growth in traditional SiP applications such as RF Front-end modules ; and (3) emerging market segments such as IoT, wearables, MEMS, sensory modules and infotainment.
To enable complex heterogeneous integration, advancements in both materials and processes are required. Substrate technologies with fine L/S, reduced dielectric thickness, and coreless design address the power consumption and lower form factor requirements, while enabling lower cost. Refinements to SMT design rules enable tighter component-to-component placement while improved molding technologies and compounds are necessary to enable lower mold cap profiles and smaller dimensions. New process technologies such as conformal shielding and compartmental shielding are also required to address electromagnetic interference (EMI) issues that are commonly encountered with the close proximity of devices integrated into the same package.
STATS ChipPAC has developed comprehensive capabilities, including design rules, advanced packaging technologies, high density SMT component placement, advanced molding for complex topographies, conformal shielding, and system level test for a wide variety of SiP and modules in multiple market segments. Depending on the application requirements and product complexity, we have developed various SiP configurations ranging from conventional 2D modules with multiple active and passive components, interconnected through flip chip, wire bonding, and SMT to more complex modules such as Package-in-Package (PiP), eWLB Package-on-Package (eWLB PoP), 2.5D and 3D solutions.

YD: Integration is the keyword in SiP technology, often requiring inclusion of heterogeneous technology. Apart from functional ICs, this means integrating also discretes and passive devices (IPD). What are the SiP integration trends that you see in the future? How is STATS ChipPAC positioned to address the need of heterogeneous integration?

SCP: With the continuous push for higher functionality and performance, thinner devices and longer battery life, SiP configurations will continue to increase in complexity. A greater level of integration and form factor reduction can often be attained by replacing the passives with integrated passive devices (IPDs) or the use of embedded passives in substrate (EPS). IPDs are a cost effective way to reduce footprint, reduce interconnection complexity, improved component tolerance, yield and reliability. STATS ChipPAC has over 10 years of experience in designing and fabricating silicon level IPDs for integrated packaging solutions which are significantly smaller, thinner and with higher performance than commercially available passive devices.

YD: Looking several years ahead, will volume still come from single die packages or could we expect majority of devices in some form of SiPs?

SCP: Moving forward, SiP will continue to evolve in volume and complexity, in co-existence with single die packages, for many years to come.

YD: As semiconductor companies are consolidating and rearranging their portfolio, the semiconductor supply chain is changing. When it comes to advanced packaging, different innovative technologies are arising, as well as different business models. IDMs are reinventing their assembly lines, while TSMC is already established and growing in an area where packaging houses used to solely dominate. Is there room for everyone? How is STATS ChipPAC positioned versus its competitors?

SCP: Yes, companies across the supply chain are changing their business models to address technology and market trends. For the OSAT industry, there are the threats of encroachment from the Foundries in WLP-based packaging. However, we see from the long-established FIWLP market that there is a place for OSATs even though Foundries can provide the same service. We expect FOWLP to be the same. Many semiconductor companies prefer to have flexibility in choosing their packaging provider and don’t necessarily want to be limited to sourcing their packaging from the same supplier as their silicon.

SiP provides a whole new TAM for the OSAT industry, and frankly, a much larger one than any losses to Foundries in the WLP-based packaging area. OSATs that are positioned to support FOWLP and SiP can be expected to do well going forward. Those that aren’t will have challenges or will be niche oriented. To that end, we expect further consolidation in the OSAT industry given that there remain >100 OSATs and only the top tier companies have the scale and financial means to pursue FOWLP and/or SiP given that these technologies are very capital intensive. STATS ChipPAC as part of the JCET Group is one of those players very well positioned to capitalize on both of these trends and we see our long lead in FOWLP as an important competitive advantage.

YD: As an established and ambitious player in the packaging market, what are the next steps for STATS ChipPAC in order to maintain progress and further development?

SCP: It is critical for us to capture the synergies we have now with the JCET Group. There are cost synergies still to be fully realized and, most importantly, is the cross-selling mentioned earlier. Progress so far is great, but there are tremendous opportunities for us in leveraging JCET’s relationships, particularly in China. Next, our FlexLineTM expansion plans driven by continued diversification of our customer base as well as some strategic customers ramping eWLB in 2016 is an area of focus. Finally, we expect to show significant traction in SiP later this year which will enable us to perform better than the market average in terms of top line revenue growth. Beyond that, we are focusing more on new market segments such as automotive and the IoT phenomenon as they develop.

YD: Is there anything else that STATS Chip PAC would like to add, for our readers on iMicronews?

SCP: With increasing customer demand for FOWLP and SIP, we expect revenue growth in the OSAT industry is likely to exceed the overall semiconductor industry growth for the next several years. This represents a major opportunity for a select few OSATs with capabilities such as advanced design rules, packaging technologies, high density SMT component placement, molded underfill for complex topographies, conformal shielding, electrical, mechanical and thermal simulation, and system level test. STATS ChipPAC is very optimistic about our strategic focus, technology, manufacturing capabilities and potential for long term business growth.

Dr. Scott Sikorski, VP of WW Product Technology Marketing, STATS ChipPAC

Dr. Scott Sikorski joined STATS ChipPAC in 2009 after a 20 year career with IBM Microelectronics during which time he held positions in R&D, Manufacturing, Product Line Management, Business Management and Marketing. Upon joining STATS ChipPAC, Dr. Sikorski was responsible for the Wirebond and Test product line areas and moved to head of Corporate Strategy in late 2012 before assuming his current position as Vice President of Product Technology Marketing in December 2014. In his current role, he is responsible for leading the company’s marketing and business development activities in advanced packaging technology. Dr. Sikorski received his Bachelor of Science degree from Columbia University’s School of Engineering and Applied Sciences in Metallurgical Engineering and his Master’s degree and Ph.D. from the Massachusetts Institute of Technology, both in Materials Engineering.

Boris Petrov, Director of Market Intelligence, STATS ChipPAC
Prior to joining STATS ChipPAC in 2010, Boris worked at leading semiconductor companies including Intel, Fairchild, Zilog, Signetics and Siemens as well as in strategy practices of leading management consulting firms such as McKinsey, Boston Consulting and Booz-Allen. He also founded his own strategy consulting firm, The Petrov Group, LLC. Boris has a Master of Science (MS) degree in Electrical Engineering from the University of Zagreb and a Master of Business Administration (MBA) degree from Stanford University.

 Source: www.yole.fr / www.statschippac.com