高通(Qualcomm) 先進工程部資深總監Matt Nowak日前指出，在使用高密度的矽穿孔(TSV)來實現晶片堆疊的量產以前，這項技術還必須再降低成本才能走入市場。他同時指出，業界對該技術價格和商業模式的爭論，將成為這項技術未來發展的阻礙。
“如果我們無法解決價格問題，那麼TSV的發展道路將更加漫長，”Nowak說。他同時指出，在價格與成本之間仍然存在的極大障礙，加上新技術的不確定性所隱含的風險，以及實際的量產需求，形成了三個TSV技術所面臨的難題。
部份業界人士認為，到2014年，智慧手機用的行動應用處理器可能會採用TSV技術，成為率先應用TSV量產的產品。JEDEC正在擬訂一個支援TSV的Wide I/O記憶體介面，其目標是成為下一代採用層疊封裝(PoP)之低功耗DDR3鏈接的繼任技術。
“可提供12.8GB/s的LPDDR3主要針對下一代層疊封裝元件應用，但Wide I/O也具有其市場潛力，”Nowak說，他同時負責高通的TSV技術部份。“技術上來說，Wide I/O可自2014年起進入應用，然而，價格和商業模式仍將是該技術發展的阻礙。”
TSV技術承諾將提升性能，同時也將降低功耗及縮小元件尺寸，以因應包括行動處理器在內的各種應用需求。
TSV的致命弱點仍然是它的成本，Nowak說。“Wide I/O DRAM的價格較現有的PoP配置高出許多，而PoP也不斷改良，甚至未來有可能設法再開發出一個新世代的產品，”他表示。
Nowak指出，一個名為 EMC-3D 的業界組織最近表示，以目前用於量產的工具模型為基礎來推估，TSV將使每片晶圓增加約120美元的成本。
目前該技術仍然缺乏明確的商業模式，而且定價問題也頗為複雜，Nowak說。例如，當晶圓廠製作完成，以及在完成封裝後，哪個環節該為良率負責？
“一些公司可以扮演整合者的角色，但未來整個商業模式可能會有稍許改變，”他同時指出，目前業界已經初步形成了一些TSV供應鏈的夥伴關係。
動機和進展
Qualcomm已經設計出一款28nm TSV元件的原型。“我們針對這項技術進行了大量的開發工作，”Nowak說。
更廣泛的說，TSV可協助半導體產業延續其每年降低30%電晶體成本的傳統。Nowak也表示，在不使用TSV技術的情況下，由於超紫外光(EUV) 延遲而不斷上升的微影成本，也對半導體產業維持微縮和進展的步伐提出嚴峻挑戰。
好消息是工程師們在解決TSV堆疊所面臨的挑戰方面時有進展。“雖然挑戰仍然很多，但至少目前我們已經建立了一些基礎和所需的專有知識，”他表示。
他同時指出，台積電(TSMC)今年度在VLSI Symposium上報告已建構出一種更好的TSV介電質襯底(dielectric liner)。工程師展示了高度深寬比(aspect ratios)為10:1的試製過孔，並減輕了外部銅材料擠壓過孔的問題。
Nowak還引用了一些背面晶圓加工、薄化晶圓的臨時托盤開發情況，並展示了有時用於取代過孔的連接微凸塊。EDA供應商也在架構工具和2D建構工具方面取得了進展。
“你可以設計一個設備來使用這些工具，”他說。
然而，目前這些工具仍然缺乏有關機械應力、封裝和晶片水準的交換資料標準。業界仍需為在TSV應用中‘大幅減少’的靜電放電水平容差定義標準，他說。
另外，業界也正在開發測試程序。“目前仍不清楚在量產時是否會使用到微探針(micro-probing)”他指出，重點是要削減成本，但“我們仍在增加測試步驟。”
編譯： Joy Teng
SANTA CLARA, Calif. – Major price reductions are needed for chip stacks using high density through-silicon vias (TSVs) before the technology can be used in high volume devices, said a Qualcomm engineering manager.
Matt Nowak, a senior director of advanced engineering at Qualcomm, reviewed progress on technology challenges for TSVs in a keynote address here. In comments after his talk, he said industry debates over prices and business models are the biggest hurdles ahead.
"TSVs are a long way off if we can't solve the price problem," said Nowak in discussion after his talk at the International Wafer-Level Packaging Conference here. "There's a big gap between price and cost, a large delta" based on uncertainties and risks of a new technology and volume demand for it, he said.
Several sources say smartphone mobile applications processors could use TSVs as early as 2014, becoming one of the first high volume applications of the technology. A Wide I/O memory interface in the works at Jedec paired with TSVs aims to be the successor of a low power DDR3 link coming for next-generation mobile processors using a package-on package (PoP) approach.
"LPDDR3 is coming along as the next clear technology for package-on-package devices offering 12.8 Gbytes/second, and somewhere beyond that Wide I/O has the potential to intersect the market," said Nowak who oversees work on TSVs at Qualcomm. "Technically Wide I/O could be used by 2014, but there are pricing and business model issues that if they are not settled will make it a moot point," he added.
TSVs promise to raise performance while lowering power and keeping device sizes low for a range of applications including mobile processors.
"The Achilles heel [for TSVs] is cost," Nowak said in his keynote. "Wide I/O DRAM is considerably more expensive than current PoP configurations, and PoP will continue to evolve and maybe find ways to squeeze one more generation out," he said.
Nowak said one industry consortium, the EMC-3D group, recently concluded TSVs will add about $120 additional cost per wafer based on its models of tools now in production. The group claims on its Web site it sees a path to prices coming down to about an extra $150 per wafer.
The lack of clear business models complicates the pricing issue, Nowak said. For example, it's still a matter of debate which parts of the process are done in a wafer fab and which in a packaging house and who will be liable for yields.
"Some companies may act as integrators and take liability--likely the model will evolve," he said, noting that some TSV supply chain partnerships already are forming.
資料來源:http://www.eetimes.com/electronics-news/4229116/Price-cited-as-top-challenge-in-3-D-stacks
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