真乄科技業的頂尖投資團隊

藍色巨人IBM宣布，未來5年將投入30億美元，旨在研發7奈米晶片，並開發矽以外的晶片材料，提升晶片效能，以滿足海量資料和雲端運算世代的需求。

在雲端時代越來越多服務和程式透過資料中心進行，而且網路世代的企業積極尋找分析龐大數據的方法。不過IBM指出，晶片技術在提升速度、體積、效率等方面，已經面臨極限。

IBM表示，公司未來5年斥資30億美元於晶片研發計畫，可望強化研究團隊在奈米電子、矽光子、新記憶體技術，和感知運算等領域的能力。

IBM系統和科技部門資深副總裁羅薩米力亞（Tom Rosamilia）表示，「隨著我們的科學家和工程師突破半導體創新的極限，開拓後矽時代的未來，往後10年的運算硬體系統將和現在有極大的不同。」

在IBM投入新的晶片研發計畫的同時，熟知內情人士透露，該公司也有意出售晶片製造部門，外傳晶圓代工廠格羅方德（Globalfoundries）成為IBM半導體事業最終買主的可能性極高。

負責IBM軟體和系統業務的資深副總裁米爾斯（Steve Mills）指出，公司重組硬體業務讓很多人質疑IBM的硬體策略，IBM不得不公開晶片計畫。

米爾斯婉拒證實IBM有意出售晶片製造部門一事，僅表示「公司持續為技術尋找更有效的方法，晶片研發計畫是IBM深入投資的領域之一。」

獨立分析師凱伊（Roger Kay）表示，IBM將現行22奈米的半導體製程提升至下一階段，所需的成本高達10億至12億美元，出脫晶片製造業務可望節省龐大開支。IBM想要展示對晶片業務的決心，同時又不想被龐大的成本困住。

We have been hearing the obituaries for complimentary metal-oxide-semiconductor (CMOS) for twenty years now. But it’s still here and holding out to the bitter end it seems. Despite needing ever more ingenious engineering twists to keep it going, CMOS will eventually fall victim toMoore’s Law as it continues its march towards ever smaller transistor dimensions.

IBM has stepped up to face this growing issue with the announcement this week that it will be spending US $3 billion over the next five years on a project it has dubbed “7nm and Beyond”.  Big Blue’s aim will be to pursue ways to bring traditional silicon-based technologies to ever smaller dimensions and simultaneously develop alternative materials, namely carbon nanotubes, graphene, and other nanomaterials.

The $3 billion is equivalent to half of all IBM's R&D expenditure last year, but others have pointed out that this amount of funding spread out over five years essentially maintains IBM's current chip research spending levels.

Nonetheless, for a company that has reportedly been trying to sell off its hardware business, this is a significant investment—whether it’s aimed at boosting the slumping hardware unit to achieve its old glory or polishing it up for a sale.

While this may be a matter of fascinating speculation for investors, the impact on nanotechnology development  is going to be significant. To get a better sense of what it all means, I was able to talk to some of the key figures of IBM’s push in nanotechnology research.

I conducted e-mail interviews with Tze-Chiang (T.C.) Chen, vice president science & technology, IBM Fellow at the Thomas J. Watson Research Center and Wilfried Haensch, senior manager, physics and materials for logic and communications, IBM Research.

Silicon versus Nanomaterials

First, I wanted to get a sense for how long IBM envisioned sticking with silicon and when they expected the company would permanently make the move away from CMOS to alternative nanomaterials. Unfortunately, as expected, I didn’t get solid answers, except for them to say that new manufacturing tools and techniques need to be developed now.

“We anticipate that in order to scale to 7 nanometers and perhaps below for the industry, we will need to have the semiconductor architectures and new manufacturing tools and techniques in place by the end of the decade,” said Chen in an e-mail interview. “That's why it is critical for us to make the significant investment now into the research and early stage development to demonstrate what 7nm innovations will be useful before it can even be commercialized.”

Top-Down versus Bottom-Up Manufacturing Techniques

I was particularly interested in the “beyond” part of the project, which implied dimensions below 7nm and where things start to get really tricky for traditional top-down manufacturing techniques, like lithography.  Despite all the continued advances, some have argued that once you get below 3nm top-down manufacturing techniques are just not viable.

I didn’t get a clear response as to whether IBM agreed with the assessment that at the 3-nm threshold top-down manufacturing fails to be effective for large scale manufacturing, but I did get the answer that IBM is pursuing both top-down and bottom-up manufacturing techniques. That’s apparent by the body of research they’ve published, but what we still don’t know is how far they intend to push lithography below 7 nm for large-scale chip production.

Carbon Nanotubes versus Graphene

In the press release, IBM provides details on two of the favored nanomaterials of the last decade: carbon nanotubes and graphene.

With carbon nanotubes (CNTs), points out its recent success at producing the material with 99.99 percent purity. To clarify, Wilfried Haensch explained: “The 99.9 percent refers to the purity with respect to semiconductor tools. It means that out of 10,000 tubes 1 is metallic and this is what you want if you want to build devices. But we need to reach 999,999 and that is part of our current focus.”

This overcomes one of the big obstacles in carbon nanotube production: ensuring you get semiconducting or metallic versions. But what about the other obstacle: aligning the CNTs?

It turns out that the two are problems are related. “There are two approaches,” says Haensch. “One is to grow the nanotubes on a wafer and then transfer them. The challenge is you loose purity for semiconductor tubes.  One-third are metallic and two-thirds are semiconductor, so the metallic ones need to be burned and then you have randomness. We take the tubes and purify them first to remove the metallic, and use a self-assembly method to place them in the positions we would like to have them.”

Finally, with graphene I wanted to know what IBM saw as the material's role in electronics, especially because it lacks an inherent band gap and must have that property engineered into the material. For this, Haensch was direct and to the point: “We see an opportunity with graphene in RF electronics. We have shown that RF circuits can be manufactured on the back end of an existing CMOS process.” Not exactly a broad set of applications for graphene in electronics.

（新聞來源：工商時報─記者顏嘉南／綜合外電報導）

Source:IEEE