在2011年超級電腦大會(SC’11)上，英特爾公布針對高效能運算(high-performance computing，HPC)所設計、內含新一代Intel Xeon處理器以及 Intel Many Integrated Core (Intel MIC)架構的平台。英特爾亦簡述在研發上的新投資計畫，期望在2018年之前帶領產業跨入百萬兆級(Exascale)運算的效能境界。
在會議簡報時，英特爾資料中心與聯網系統事業群技術運算部總經理Rajeeb Hazra指出：「Intel Xeon處理器E5系列是全球首顆支援完全整合PCI Express 3.0規格的伺服器專用處理器。PCIe 3.0不僅提供較PCIe 2.0高2倍的互連頻寬，還帶來功耗更低且密度更高的伺服器建置組態。新的架構控制器(fabric controllers)受惠於PCI Express 3.0規格的優勢，能更有效率地控制效能，並加快資料傳輸，以因應HPC超級電腦中持續增加的節點。」
初期的效能測量數據顯示，相較於前一代的Intel Xeon 5600處理器系列，Intel Xeon E5處理器在FLOPS(以Linpack測得的每秒浮點運算效能)方面高出2.1倍，在執行實際HPC運算作業方面的效能則高出70%。
Hazra表示：「客戶對Intel Xeon E5處理器的接受度超出我們的預期，讓這顆處理器以最快的速度登上TOP500排行榜，其上榜速度甚至超越英特爾史上所有其他處理器。對於現今的科學研究而言，收集、分析與分享大量的資訊至關重要，因此需要超越以往的處理器效能、以及能搭配針對這方面用途量身打造的技術。」
正當Intel Xeon E5處理器一路搶進TOP500排行榜之際，今年適逢全球首顆微處理器(Intel 4004處理器)問市40週年，也是Intel Xeon品牌推出的10週年。自從Intel Xeon處理器在2001年推出以來，英特爾預計該處理器的效能已提升超過130倍。
在首次出貨給超級電腦中心之後的兩個月內，內含Intel Xeon E5處理器的系統已在TOP500排行榜佔了10個席位。超過2萬顆該款處理器正在運算，所累計的尖峰效能超越3.4 Petaflop。
如先前所宣布，即將推出的Intel Xeon處理器E5系列將為許多未來新組建的超級電腦採用，其中包括德州先進運算中心(Texas Advanced Computing Center) 10 PFLOPS運算等級的“Stampede”、美國國家大氣研究中心(The National Center for Atmospheric Research) 1.6 PFLOPs運算等級的“Yellowstone”、 法國國家高效能運算中心(GENCI) 1.6 PFLOPS運算等級的“Curie”、國際核融合能源研究中心(International Fusion Energy Research Center，IFERC) 1.3 PFLOPS運算等級的系統、以及美國航太總署(NASA)超過1 PFLOPS運算等級的“Pleiades”。
英特爾於9月已開始向少量的雲端與HPC客戶供應Intel Xeon®處理器E5系列，預計將於2012上半年開始大量供貨。英特爾預期將有400款內含Intel® Xeon®處理器E5系列的系統設計，數量幾乎是Xeon®5500/5600處理器世代的一倍。初期投產階段的需求較前一代Intel Xeon 5500或5600系列處理器多了約20倍。
在2011年超級電腦大會中，英特爾也公布了大幅擴充的伺服器主機板與機箱的細節資訊，其中包括特別針對HPC進行最佳化的產品，這些方案都將支援Intel Xeon處理器E5。
英特爾亦重申其承諾，將針對高度平行處理的應用，提供最具效率且容易編程的平台。Intel MIC架構的效益涵蓋許多應用領域，包括氣象模型、斷層攝影、蛋白質折疊結構、以及先進材料模擬等應用，都在2011年超級電腦大會的英特爾攤位上展示。
英特爾首次在現場展示代號為 “Knights Corner”的 Intel® MIC架構協同處理器，展現了英特爾架構能帶來超過1 TFLOP的雙倍精準度浮點運算效能(測量基準為雙倍精準度的一般矩陣乘法——DGEMM*)。這是單一處理晶片首度能在現場展示達到如此高的效能。
Hazra表示：「英特爾於1997年在Sandia實驗室的“ASCI RED”系統中，首次展示內含9,680顆Intel Pentium Pro處理器的Teraflop等級超級電腦。如今能在一顆內含Intel MIC架構的晶片中獲得如此高的效能，無疑是重大里程碑，將再次被記載於HPC的重要歷程中。」
“Knights Corner”是第一個商業化的Intel MIC架構產品，將採用英特爾最新3-D三閘(Tri-Gate)電晶體與22奈米(nm)製程，並內含超過50個核心。正式問市時，Intel MIC產品不僅將採用專為處理高度平行作業所設計的架構來提供超高效能，還能相容於現有的x86編程模式與工具。
Hazra表示：「“Knights Corner”協同處理器相當獨特，它不同於傳統的加速器，不僅可完全存取，而且可加以編程，本身就像功能完整的HPC運算節點，應用程式會把它視為執行Linux作業系統的電腦本身，獨立於主機作業系統之外。」
Intel® MIC架構的其中一項優勢就是能執行現有的應用程式，而且不必把程式碼移植到新的編程環境。這將讓科學家能同時運用CPU與協同處理器的效能，加速執行現有的x86應用程式，進而大幅節省時間、成本、以及資源，免去用專利語言重新撰寫程式的麻煩。
正如先前在德國漢堡舉行的2011年國際超級電腦會議(International Supercomputing Conference)中所宣布，英特爾的目標是在2018年提供百萬兆級運算的效能(比目前的效能高出100倍以上)，而且消耗電力僅是現今頂尖超級電腦的兩倍。要達到這項目標的基礎，必須和HPC業界緊密地合作，而今天Hazra宣布的多項新計畫，將有助於達成這項目標。
英特爾與巴塞隆納超級電腦中心(Barcelona Supercomputing Center，BSC)已簽署跨年度的協議，將在巴塞隆納設立百萬兆級實驗室，這是英特爾在歐洲設立的第四座百萬兆級研究實驗室，前三座分別設在法國巴黎(Paris)、德國尤利希(Juelich)、以及比利時魯汶(Lueven)。新實驗室專注於研究百萬兆級的超級電腦在編程與執行階段系統方面的擴充問題。
此外，英國的科學與技術設施委員會(Science and Technology Facilities Council，STFC)與英特爾已簽署備忘錄，雙方將共同開發與測試相關技術，打造未來的超級電腦。在這項初期協議的規範下，STFC位於英國Daresbury實驗室的運算科學家將與英特爾合作，針對英特爾目前與未來的硬體以及領先業界的軟體應用進行測試與評估，以確保科學家能妥善運用未來的英特爾超級電腦系統。
於2011年超級電腦大會上公布的第38版TOP500排行榜，展現了全球頂尖科學家與機構持續採用Intel Xeon處理器打造其超級電腦。和前一版排行榜相較之下，在所有新進榜的超級電腦中，內含英特爾核心的超級電腦佔了將近85%。Intel Xeon 5600系列處理器是清單中的佼佼者，共有223部系統採用此款處理器。Intel Xeon處理器E5系列初被採用即獲得排行榜中的10個席位，而且刷新記錄，每個插槽達到152 GFLOPS的效能與91%的效率。英特爾處理器在前10大排行榜中佔了5個席位，在所有登榜的超級電腦中佔了將近77%的席位。完整報告內容請瀏覽www.top500.org。
Intel Reveals Details of Next-Generation High-Performance Computing Platforms
Intel® Xeon® E5 Processor Debuts on TOP500 List; First Intel® Many Integrated Core Co-processor Demonstrated to Deliver Performance Above 1 TFLOPS
NEWS HIGHLIGHTS
Intel® Xeon® processor E5 family, world's first server chip to support the PCI Express* 3.0 I/O integration, debuts on TOP500 list, powering 10 supercomputers.
Intel's "Knights Corner" product, the first commercial co-processor based on the Intel® Many Integrated Core (Intel® MIC) architecture, was shown for the first time breaking the barrier of 1 TFLOPS double precision performance**.
Intel announced additional investments and new partner projects with R&D laboratories to pursue the goal of achieving Exascale performance by 2018.
Intel processors power 85 percent of all new entries to the latest TOP500 list of supercomputers, with Intel Xeon processor 5600 series being most popular selected for 223 systems.
SEATTLE--(BUSINESS WIRE)--At SC11, Intel Corporation revealed details about the company's next-generation Intel Xeon processor-based and Intel® Many Integrated Core (Intel® MIC)-based platforms designed for high-performance computing (HPC). The company also outlined new investments in research and development that will lead the industry to Exascale performance by 2018.
During his briefing at the conference, Rajeeb Hazra, general manager of Technical Computing, Intel Datacenter and Connected Systems Group, said that the Intel Xeon processor E5 family is the world's first server processor to support full integration of the PCI Express 3.0 specification**. PCIe 3.0 is estimated** to double the interconnect bandwidth over the PCIe* 2.0 specification** while enabling lower power and higher density server implementations. New fabric controllers taking advantage of the PCI Express 3.0 specification will allow more efficient scaling of performance and data transfer with the growing number of nodes in HPC supercomputers.
The early-performance benchmarks revealed that the Intel Xeon E5 delivers up to 2.1* times** more performance in raw FLOPS (Floating Point Operations Per Second as measured by Linpack*) and up to 70 percent more performance using real-HPC workloads compared to the previous generation of Intel Xeon 5600 series processors.
"Customer acceptance of the Intel Xeon E5 processor has exceeded our expectations and is driving the fastest debut on the TOP500 list of any processor in Intel's history," said Hazra. "Collecting, analyzing and sharing large amounts of information is critical to today's science activities and requires new levels of processor performance and technologies designed precisely for this purpose."
The Intel Xeon E5 processors made their way onto the TOP500 list in the year of the 40th anniversary of availability of the world's first microprocessor (the Intel 4004 processor) and on the 10th anniversary of the launch of the Intel Xeon brand. Since the introduction of Intel Xeon processors in 2001, Intel estimates that Xeon processor performance has increased by more than 130 times***.
Two months since its initial shipments to supercomputer centers, Intel Xeon E5 processors now power 10 systems on the TOP500 list. More than 20,000 of these processors are in operation, delivering a cumulative peak performance of more than 3.4 Petaflops.
As previously announced, the upcoming Intel Xeon processor E5 family will power several other future supercomputers, including the 10 PFLOPS "Stampede" at Texas Advanced Computing Center, the 1.6 PFLOPs "Yellowstone" at The National Center for Atmospheric Research, the 1.6 PFLOPS "Curie" at GENCI, the 1.3 PFLOPS system at International Fusion Energy Research Center (IFERC) and more than 1 PFLOPS "Pleiades" expansion at NASA.
Intel started shipping the Intel Xeon processor E5 family to a small number of cloud and HPC customers in September, with broad availability planned in the first half of 2012. Intel is tracking more than 400 design wins for the Intel Xeon processor E5 family, nearly double the amount at time of launch of the Xeon 5500/5600 generation. Demand for initial production units is approximately 20 times greater than for previous generations of the Intel Xeon 5500 or 5600 series processors.
During SC'11 Intel also provided details on its greatly expanded lineup of server boards and chassis, including products specifically optimized for HPC, which will be ready to support the launch of the Intel® Xeon® Processor E5.
First Teraflops Intel Many Integrated Core Co-Processor Showcased
Intel also reiterated its commitment to delivering the most efficient and programming-friendly platform for highly parallel applications. The benefits of the Intel MIC architecture in weather modelling, tomography, proteins folding and advanced materials simulation were shown at Intel's booth at SC'11.
The first presentation of the first silicon of "Knights Corner" co-processor showed that Intel architecture is capable of delivering more than 1 TFLOPs of double precision floating point performance (as measured by the Double-precision, General Matrix-Matrix multiplication benchmark -- DGEMM*). This was the first demonstration of a single processing chip capable of achieving such a performance level.
"Intel first demonstrated a Teraflop supercomputer utilizing 9,680 Intel® Pentium Pro® Processors in 1997 as part of Sandia Lab's "ASCI RED" system," Hazra said. "Having this performance now in a single chip based on Intel MIC architecture is a milestone that will once again be etched into HPC history."
"Knights Corner," the first commercial Intel MIC architecture product, will be manufactured using Intel's latest 3-D Tri-Gate 22nm transistor process and will feature more than 50 cores. When available, Intel MIC products will offer both high performance from an architecture specifically designed to process highly parallel workloads, and compatibility with existing x86 programming model and tools.
Hazra said that the "Knights Corner" co-processor is very unique as, unlike traditional accelerators, it is fully accessible and programmable like fully functional HPC compute node, visible to applications as though it was a computer that runs its own Linux*-based operating system independent of the host OS.
One of the benefits of Intel MIC architecture is the ability to run existing applications without the need to port the code to a new programming environment. This will allow scientists to use both CPU and co-processor performance simultaneously with existing x86 based applications, dramatically saving time, cost and resources that would otherwise be needed to rewrite them to alternative proprietary languages.
Intel Increases Investment in Exascale Computing Labs
As previously announced at the International Supercomputing Conference 2011 in Hamburg, Germany, Intel's goal is to deliver Exascale-level performance by 2018 (which is more than 100 times faster performance than is currently available) while only requiring two times the power usage of the current top supercomputer. Fundamental to achieving that goal is working closely with the HPC community, and today Hazra announced several new initiatives that will help to achieve that goal.
Intel and the Barcelona Supercomputing Center (BSC) have signed a multi-year agreement to create the Exascale Laboratory in Barcelona, Intel's fourth European Exascale R&D lab that joins existing sites in Paris, Juelich (Germany) and Lueven (Belgium). This new laboratory will focus on scalability issues in the programming and runtime systems of Exascale supercomputers.
Additionally, the Science and Technology Facilities Council (STFC) and Intel have signed a memorandum of understanding to develop and test technology that will be required to power the supercomputers of tomorrow. Under this initial agreement, STFC's computational scientists at its Daresbury Laboratory in England and Intel will work together to test and evaluate Intel's current and future hardware with leading software applications to ensure that scientists are ready to exploit Intel's supercomputer systems of the future.
TOP500 Supercomputers
The 38th edition of the Top500 list, which was announced at SC'11, shows that the world's leading scientists and institutions continue to base their supercomputers on Intel Xeon processors. Out of all new entries to the list compared to last edition, Intel-powered supercomputers accounted for close to 85 percent. The Intel Xeon 5600 series processor is the top processor on the list, powering 223 systems. Intel Xeon processor E5 family made its introduction in 10 systems on the list with record-breaking 152 GFLOPS per socket and 91 percent efficiency. Intel processors also power five systems in the top 10 and almost 77 percent of all listed supercomputers. The complete report is available at www.top500.org.
More information on SC'11, including Hazra's presentation and pictures, are available at www.intel.com/newsroom/sc11.
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