真乄科技業的頂尖投資團隊

3D IC integration is always on the menu at imec, with program director for 3D system integration Eric Beyne presenting imec’s latest packaging experiments and warning us about hidden yield costs.

Imec has proven the suitability of tin-tipped 20µm pitch copper µBump interconnects and backside revealed copper TSVs to be used as µBump for multiple die stacking up to six layers. But thermal management remains a limitation for stacking dies as power density increases too, warned Beyne, not just for processors but also for DRAM whose data retention decreases with temperature. 

So an alternative stacking option is to link multiple dies on an interposer, with fine pitch interconnects. The interposer technology to be used is very cost sensitive, what’s more, the longer interconnects increase resistive losses and delays, adding capacitance too.

Based on Wide-I/O memory-logic interconnects requirements respecting the Jedec Standard JESD229 (1200 µBumps per chip, four 128-bit channels consisting of 6 rows with 40 µm pitch by 50 columns of 50 µm pitch), imec compared simulated various approaches on a 10x20mm interposer. An advanced high density laminate build-up with line sections of 10x10µm linked by vias 15µm in diameter took 8 routing layers with an average wire length taking more than 80% of the die spacing.

A semi-additive copper and photo-patterned dielectric redistribution layer build-up with line sections of 5x5µm and vias 7µm in diameter, took half the number of routing layers with an average wire length over 66% of the die spacing. 

The finer silicon interposer option, using a back-end-of-line (BEOL) copper/oxide damascene technology with line sections of 1x1µm and 1µm vias only required two routing layers and the average wiring length was equal to the die spacing on the interposer. 

Imec has validated its BEOL copper/ oxide damascene silicon interposer technology at 200Mbit/s by connecting real chips with 2x2µm copper tracks, with excellent eye diagrams. 

The trade-off between vertical 3D stacking and side-by-side die stacking on an interposer has to be carefully evaluated, explained Beyne, not just for performance, but also for the costs associated with different testing, assembly and logistics scenarios and the overall yield results. 

The test flow of each stacking option must be optimized based on yield and cost parameters of the individual components being assembled. This evaluation and the optimization of the 3D stacked IC test flow is not trivial, costs can soar if the yield drops due to inadequate testing steps. 

For this purpose the Delft University of Technology (TU Delft) and imec have co-developed 3D-COSTAR, a test flow cost modelling tool for 2.5/3D stacked ICs. The tool may also hint at extra design-for-test features that may need to be integrated at the design stage of the different chips. The tool covers the entire 2.5D-/3D-stacked IC production flow, including design, manufacturing, test, packaging and logistics. It is aware of the stack build-up (2.5D versus 3D, multiple towers; face-to-face or face-to-back) and stacking process (die-to-die, die-to-wafer, or wafer-to-wafer). 

Source:Julien Happich http://www.electronics-eetimes.com/en/3d-versus-2.5d-ic-stacks-beware-of-hidden-yield-costs-says-imec.html?cmp_id=7&news_id=222918598&vID=44