真乄科技業的頂尖投資團隊

STATS ChipPAC is now the world leader in the packaging of devices using FOWLP, with a good existing customer base and a very strong pipeline of projects. As published in the new report from Yole Développement "Fan-Out and Embedded Die: Technologies & Market Trends", Yole analysts are expecting a growth of 30% per year for the next 5 years. At the early days, STATS ChipPAC and Nanium were the only players in that field; now multiple companies are willing to support this platform, including OSAT, specialized packaging house and even front end foundries. 
Now it is the time to discover with Dr. Seung Wook Yoon, Deputy Director, Product Technology Marketing, STATS ChipPAC, how the company has structured its activities, development and manufacturing infrastructure in order to take full benefit of this growth.

Yole Développement: Could you please introduce STATS ChipPAC activities in general and its involvement in the Fan Out packaging platform?
Seung Wook Yoon: STATS ChipPAC has been actively developing embedded packaging technology for over 10 years. We were the first OSAT to fabricate integrated passive devices on silicon and establish an R&D facility dedicated to developing advanced integration technology including through silicon via (TSV) and embedded die packaging. When Infineon introduced the first generation of eWLB in 2007, we viewed this as a dynamic technology with the scalability to address the demand for rapidly increasing I/O densities in smaller semiconductor packages. eWLB quickly became an important cornerstone of our wafer level portfolio and we have taken a strong leadership position in driving technology and manufacturing innovations for next generation FOWLP technology.

YD: Market of FOWLP has been rather flat last year but a new growth is expected and starting. Do you agree with that and could you explain us why?
SWY: Yes, we do expect to see growth this year in baseband processors, RF transceivers, connectivity, security device and power management ICs where there has been a steady customer adoption and in new opportunities such as MEMS, fingerprint sensors and wearable electronics. Over the longer term horizon, we expect to see growth opportunities in memory and advanced application processors.

YD: What are the applications pulling the market? What are their requirements?
SWY: For baseband processors, RF transceivers, power management ICs, MEMS and sensors in mobile applications, FOWLP provides ultra-high density interconnection, superior electrical performance and ability to route multiple die in a cost effective, low-profile package. FOWLP in a 3D PoP configuration has received considerable customer interest for memory and advanced application processors by virtue of the higher routing density and form factor reduction. The requirement for System-in-Package (SiP) integration is also a growing trend for advanced application processors, MEMS and sensors in wearable electronics as way to cost effectively achieve advanced silicon die partitioning for increased performance and integration in a reduced form factor.

YD: What are the advantages of FOWLP for these applications versus other packages?
SWY: The advancement of silicon scaling below 20nm in reaching higher performance, higher bandwidths and lower power consumption in next generation applications is pushing the boundaries of packaging requirements to higher I/O densities with finer line/spacing as well as improved electrical performance and passive embedded technology capabilities. Traditional packaging technologies lack the scalability to address these requirements. In comparison to emerging technologies, FOWLP has found success in 2.5D and 3D integration (including Si partitioning) as a more cost effective and infrastructure-friendly alternative to emerging technology such as TSVs.

YD: Different innovative technologies of Fan-Out are showing up (Deca Technologies' adaptive patterning, J-Devices' panels) and important players are getting more involved (TSMC, SPIL): Is there room for everyone? How eWLB is positioned versus those technologies?
SWY: With 6 years of HVM experience, eWLB is the only proven manufacturing FOWLP solution. It has proven its reliability, yield and scalability with major mobile chip customers. More FOWLP technologies are currently being developed, but are not in volume production yet. However, the increase in development activities for fan-out shows the importance of this technology and the future growth potential of FOWLP. We are working on further advancements in the design flexibility, performance and package integration as well as further cost effectiveness that is possible with the scalability of panel manufacturing.

YD: What are the packaging integration trends? Volume will come from single dies packages or market will ask more and more for SiP? What is your strategy to follow these trends?
SWY: STATS ChipPAC has already been in HVM for the last 3 years on multi-die eWLB and qualified several customers on RF, SoC, PMIC and memory devices. Discrete MLCC and integrated passive embedding also were successfully demonstrated and qualified. As discussed previously in the PoP session, SiP- eWLB is one of the attractive solutions for miniaturized module and 3D packaging in mobile, wearables and IoT products.

YD: What is your roadmap to address market needs? (L/S, package thickness, number of RDL, etc...)
SWY: STATS ChipPAC's roadmap is quite well aligned with our customers' needs and current market trends. We are working on further enhancements for highly integrated eWLB packaging solutions. To achieve this, we are developing smaller LS/LS down to 2/2um, ultra thin package profiles (currently qualified for 0.3mm including solder ball) and multi-layer RLD (above 3 layers). STATS ChipPAC is in high volume production on 28 nm Si node and starting to ramp 20 nm devices. The larger panel carrier sizes that can be utilized with our FlexLineTM approach will be the key driver for further cost reductions in FOWLP. STATS ChipPAC already qualified HD (high density) manufacturing capabilities and are working toward UHD (ultra high density) carrier sizes.

YD: Customers are permanently asking for lower price. That price shrink goes through cost reduction and that can be achieved thanks to larger substrate. How do you see the trend in that? Are 330mm wafers or panels going to spread? When?
SWY: As production volume has increased for FOWLP, a number of important optimizations in the manufacturing infrastructure and process have evolved into the new FlexLineTM method which we introduced in 2014. With FlexLineTM, we are able to accommodate both fan-out and fan-in devices such as WLCSP on the same manufacturing line, driving higher economies of scale and a lower manufacturing cost. The FlexLineTM process lends itself to the use of significantly larger panel sizes which provides a compelling cost reduction on a per unit basis for both fan-out and fan-in wafer level devices.

YD: You are one of the only OSATs with very high volume for Fan-Out. Do you think this situation will remain in the future or do you expect competition to go for high volume too? Is lack of multi-sourcing a challenge for customers?
SWY: Although one of the initial challenges with FOWLP adoption was the concern with multi sourcing, increased customer adoption and high volume production has brought more suppliers into the mix, making the technology more prevalent with multiple sources available. This has also triggered interest among the leading equipment manufacturers to participate in the associated equipment business.