真乄科技業的頂尖投資團隊

受智能手機、智能卡和堆疊封裝等消費類應用驅動，近年來對薄晶圓的需求日益增長。

據估算，2015年，用於MEMS器件、CMOS圖像傳感器、應用矽通孔（TSV）技術的存儲器和邏輯器件以及功率器件的薄晶圓數量超過了1650萬片，這個數量相當於8英寸晶圓投入總片數（wafer starts per year, WSPY）。這些薄晶圓主要貢獻於CMOS圖片傳感器，其次是功率器件。2015年到2020年期間，薄晶圓的複合年增長率預計為14%，預計到2020年，薄晶圓的數量將達到峰值的3200萬片，相當於2020年8英寸晶圓投入總片數。

更薄的晶圓能夠帶來眾多好處，包括超薄的封裝，以及由此帶來更小的尺寸外形，還包括改善的電氣性能和更好的散熱性能。

某些應用，如存儲器和功率器件，它們的微型化朝著更小的尺寸、更高的性能以及更低的成本方向發展，這些應用的薄晶圓厚度小於100µm或甚至小於50µm。

本報告按厚度和應用分析預測了薄晶圓的需求數量。同時也包括按晶圓尺寸分析預測了晶圓減薄所使用的設備數量，以及影響上述應用的技術要點分析。

薄晶圓正催生磨削、化學機械拋光以及濕法/干法蝕刻設備產業的市場增長

現階段，最常規的半導體應用減薄工藝為磨削，所減薄晶圓的平均起始厚度為750μm到120µm。然而，厚度低於100 μm的矽晶圓會變得非常柔軟有彈性，受迫於大批量加工製造的壓力，僅僅憑藉標準的磨削方法將厚度小於100 µm的矽晶圓進一步減薄，是非常具有挑戰性的。

不同厚度的晶圓減薄所面臨的技術問題

存儲器和邏輯器件等領域需要額外的減薄步驟，如運用化學機械拋光（CMP）來消除由標準化磨削加工所引起的晶圓微開裂和邊緣崩裂。背照式CMOS圖像傳感器是唯一使用濕法/干法蝕刻處理和化學機械拋光（CMP）的應用，因為背照式CMOS圖像傳感器需要最多步驟的背面磨削工藝來確保最好的芯片質量。

TAIKO工藝是由迪思科科技有限公司（以下簡稱DISCO）開發的新型晶圓背面磨削技術。這是功率器件應用的最重要的減薄工藝之一，可用於650V-1200V IGBTs器件和40V-100V MOSFETs器件的背面金屬化層的減薄。TAIKO工藝已經應用到英飛凌和意法半導體等功率器件主要製造商的大批量生產中。

本報告提供了需要薄晶圓加工的存儲器、邏輯器件、MEMS、RFID、CMOS圖像傳感器和功率器件等應用的詳細分析。報告還按晶圓尺寸、市場營收以及上述應用所需的減薄設備類型，對若干減薄處理應用的設備進行了詳細分析。

不同應用所要求的晶圓厚度

市場對更薄的晶圓和性能更強勁的芯片的需求增長，驅動晶圓切割（劃片）技術發展

2015年，晶圓切割（劃片）設備市場規模為1億美元，預計2020-2021年，該市場的市場規模將翻倍。但是，薄晶圓加工對晶圓切割設備的濃厚興趣同時也為該行業帶來許多新的挑戰，如芯片斷裂、破片、芯片強度低、其它待處理問題和切割破損。

最常用的運用於存儲器、邏輯器件、MEMS、RFID和功率器件的切割技術是機械切割，也被稱為刀片切割。然而，市場普遍要求更薄的晶圓和更小的器件，使我們關注到市場對替代切割技術的應用趨勢，這些替代技術包括隱形切割和基於深反應離子蝕刻技術的等離子切割。

主要晶圓切割技術

存儲器主要依賴於刀片和激光切割的結合來分割複雜的堆棧。因為金屬密度高，頂層只使用刀片分割將導致脫層問題。然而，即使結合激光切割也很難安全地分割50µm的薄晶圓，這給了等離子切割“可乘之機”。

在MEMS器件領域，刀片切割主要運用於ASIC、封蓋和MEMS傳感器的分割。然而，切割工藝流程中的晶圓暴露，可能會污染傳感器並破壞敏感的MEMS結構，比如MEMS麥克風的切割，在這種情況下，大批量生產已經開始應用隱形切割來避免上述問題。

等離子切割如今也應用於MEMS器件和RFID的小批量生產，來降低芯片過於脆弱的問題，從而增強芯片強度，增加每片晶圓的芯片數量，最終降低設備所有者的整體成本。受益於刀片切割產品，DISCO在切割設備市場處於領先地位，緊隨其後的是東京精密公司（Accretech），東京精密則在隱形切割市場佔據主導地位。然而，它們的市場地位可能面臨著已經開發出等離子切割設備的Plasma Therm、Orbotech/ SPTS和松下（Panasonic）的挑戰。這一具有前景的技術將在半導體領域快速增長，並有可能重塑切割市場格局。

以功能需求為基準，本報告綜合概述了幾大應用領域所使用的關鍵切割技術，這些應用領域包括存儲器、邏輯器件、MEMS器件、RFID、CMOS圖像傳感器和功率器件。此外，報告還分別按晶圓尺寸、應用類型和切割技術，對若干切割設備進行了詳細分析。報告描述了相關的技術突破和製造工藝流程。對上述應用中都使用的特定切割設備，還進行了重點分析。

全球晶圓切割設備主要供應商

報告詳細分析了市場競爭趨勢，並提供切割市場主要設備和材料供應商的競爭格局和競爭力分析。

受市場對更薄晶圓和更強勁芯片的需求增長驅動，切割技術正在發生演變-2015年狀況

THINNED WAFERS ARE CREATING GROWTH IN THE GRINDING, CMP AND WET/DRY EQUIPMENT INDUSTRY

Strong demand for thinner wafers and smaller die is driving the evolution of dicing technologies

DEMAND FOR THINNED WAFERS IS GROWING STRONGLY!

Driven by consumer applications such as smartphones, smart cards and stacked packages, the demand for thinned wafers has increased over recent years.

We estimate that the number of thinned wafers used for MEMS devices, CMOS Image Sensors, memory and logic devices, including those with TSVs, as well as and Power devices exceeded the equivalent of 16.5 million 8-inch wafer starts per year (WSPY) in 2015. This is mainly supported by CMOS Image Sensors, followed by Power devices. We expect that this number of thinned wafers will peak at the equivalent of almost 32 million 8-inch WSPY by 2020. This would represent a 14% compound annual growth rate (CAGR) from 2015 to 2020.

Thinner wafers bring several benefits, including enabling very thin packaging, and therefore better form factors, improved electrical performance and high heat dissipation.

Miniaturization towards smaller, higher-performing, lower-cost device configurations has thinned wafers below 100 µm or even 50 µm for some applications, such as memory and power devices.

Forecasts for the number of thinned wafers by thickness and by application are analyzed in this report. It also includes insights on the number of thinning tools, breakdowns by wafer size, and technological highlights affecting the applications mentioned above.

Today, grinding is the most conventional thinning process used by semiconductor applications, reducing wafers from an average starting thickness of 750 μm to 120 µm. However, below 100 µm silicon wafers become very flexible and challenging to thin down further using only standard grinding methods due to stress in high volume manufacturing production.

Segments such as memory and logic require additional thinning steps such as chemical-mechanical planarization (CMP) in order to remove micro cracking and edge chipping caused by the standard grinding process. Backside illuminated CMOS Image Sensors are among the only applications using wet/dry processes and CMP since they need the maximum number of back grinding process steps to obtain the best die quality possible.

The TAIKO process is a new wafer back grinding method developed by DISCO. It is one of the key thinning processes used in Power devices, for the backside metallization layer for 650V-1200V IGBTs and 40V-100V MOSFETs. TAIKO has already entered mass production in power devices from key manufacturers like Infineon or ST Micro.

The report provides a detailed analysis of applications such as memory, logic, MEMS, RFID, CMOS Image sensors as well as Power devices requiring thin wafer processes. It will include insights on a number of tools, breakdowns by wafer size and revenue, and by type of thinning equipment for the applications mentioned above.

DRIVEN BY RISING DEMAND FOR THINNER WAFERS AND STRONGER DIE, DICING TECHNOLOGY IS EVOLVING

Reaching more than $100M in 2015, the dicing equipment market will double by 2020-2021. Yet at the same time thin wafers are creating new challenges of significant interest in the dicing equipment industry such as die breakage, chipping, low die strength, handling issues and dicing damage.

Today, the most common dicing technology applied across memory, logic, MEMS, RFID and power devices is mechanical dicing, also known as blade dicing. However, needs for thinner wafers and smaller devices in general, we see a trend towards adopting alternative dicing technologies. These include stealth dicing and plasma dicing based on deep reactive ion etching technology.

Memory specifically has predominantly relied on a combination of blade and laser dicing applied together to singulate complex stacks. Using only blade dicing on top layers leads to delamination issues because of the high metal density. However, it’s difficult to safely singulate 50 µm thin wafers even with laser dicing and this could allow plasma dicing to enter this area.

In MEMS devices blade dicing is largely applied for singulating the ASIC, capping and MEMS sensors. However, exposure to water from the process can contaminate some sensors and destroy sensitive MEMS structures, example in MEMS microphones. In such cases, stealth dicing has been already adopted in large volume production.

Plasma dicing has also been adopted in low volume production today for MEMS devices and RFID to reduce die fragility, boost die strength, increase the number of chips per wafer and thus reduce Cost Of Ownership of equipment overall. DISCO has a strong lead in the dicing equipment market, driven by their blade dicing products. They’re followed by Accretech, which has the dominant position in stealth dicing. However, they might be challenged by Plasma Therm, Orbotech/SPTS and Panasonic who have developed plasma dicing tools. This promising method will grow in the semiconductor area and could reshape the dicing landscape.

This report presents a comprehensive overview of the key dicing technologies used for memory, logic, MEMS devices, RFID, CMOS Image sensors as well as power devices and benchmarks them in terms of feature requirements. In addition, it includes insights into the number of tools, broken down by wafer size, by application and by dicing technology. It describes associated technological breakthroughs and manufacturing processes. More insights are included on specific dicing tools for all applications mentioned above.

Competition trends are carefully analyzed and presented as both a competitive landscape and competitive analysis of the major equipment and materials suppliers involved in the dicing market.

Source:YOLE