PTI WLP factory in Hsinchu Science Park (Courtesy of PTI)
Fan-out, the fastest-growing advanced packaging technology, will continue to grow at a CAGR of 55% for a $2.4B market by 2020. Mobile/wireless will remain the key driver, but other applications like consumer, automotive, and industrial will also see high growth. For more information see Yole Développement’s report, Fan-Out and Embedded Die: Technologies & Market Trends.
Processing fan-out on a panel scale will bring enormous cost benefits due to economies of scale, and many OSATs and equipment/materials suppliers are currently involved in the development of a fan-out on panel process. With companies like ASE Group and PTI soon entering production, we expect the market for fan-out on panel to reach ~ $160M by 2020 (see Yole Développement’s report, Status of Panel-Level Packaging & Manufacturing). We spoke with PTI’s CTO David Fang about fan-out’s potential and where PTI is headed over the next two years.
Yole Développement: Could you please introduce PTI, as well as its history and evolution?
David Fang: Powertech Technology Inc. (PTI) was founded in 1997 as a provider of DRAM packaging and testing services. In 2002 we entered the NAND Flash turnkey service, and in 2007 we branched out into logic packaging and testing. In 2008 we were ranked #5 in WW OSAT, a position we have held ever since. We support our initiatives with manufacturing facilities in Taiwan, China, and Singapore.
PTI announced its arrival as a forward-thinking technology company by establishing a technical center in 2005, developing fine pitch flip-chip packaging (licensed from IBM) in 2007, and entering 3DIC TSV advanced packaging in 2009. Today, PTI is a technology and solutions provider of IC back-end service in the OSAT market. In addition to 3DIC TSV, our services cover a wide range of packaging portfolios, metal-frame types, laminated-types, WLP, fan-out, and 2.5D packages.
Yole Développement: Nowadays there is much interest in fan-out packaging technology for industrial, and many players (OSATS as well as foundries) are involved. As a key OSAT player, how is PTI positioned in this segment?
DF: As one of the key OSAT players, PTI seeks a total solution that meets the requirements of all its customers. Since fan-in WLP is limited by I/O counts, PTI has invested much time and resources into fan-out packages in order to resolve these concerns.
Yole Développement: PTI is working on fan-out on panel. What is the expected timeline for production (HVM)? Briefly explain the manufacturing readiness for fan-out on panel.
DF: PTI has been working on a panel-size solution for fan-out with tool vendors for over two years. After our new production facility is completed in July 2016, the tools will be installed in Q3 2016. The process setup, integration, and qualification are targeted for completion by the end of Q1 2017, and production will begin by Q2 2017.
Yole Développement: How much cost reduction do you expect by moving fan-out from wafer to a panel format? Apart from cost, what are the other advantages of manufacturing fan-out on panel?
DF: The expected cost reduction of the panel format relative to wafer fan-out is 30% - 40%. The exact number will depend on the package size and design.
Yole Développement: Most players have invested in a 300mm or 330mm wafer line for fan-out. Do you think that the market is sufficient for fan-out on panel?
DF: Industries prefer to maximize the use of their existing processing equipment, so for this reason they have invested in 300mm or 330mm wafer lines. However, we believe that the cost, throughput, and application potential of panel fan-out solutions will attract increasing interest from equipment suppliers. The growth of fan-out on panels is expected.
YD: Fan-out on panel requires different equipment and materials compared to wafer. Do you think the supply chain is ready for this?
DF: The greatest challenge for fan-out on panels is the readiness of equipment suppliers. After some initial resistance and several years of promotion and breakthroughs in the technology, suppliers are now eagerly embracing fan- out on panels.
We believe that the industry is watching PTI’s panel-level fan-outs and that the technology’s popularity will increase once it succeeds.
Fan-Out panel sample (Courtesy of PTI)
YD: Many players are working on panel-level fan-out using WLP/PCB/display/photovoltaic or mixed infrastructure. What infrastructure are you leveraging for fan-out on panel?
DF: PTI’s panel-level fan-out leverages a mixed infrastructure.
YD: Which major applications will adopt fan-out on panel? Do you think advanced application processors for mobile will move from wafer to panel fan-out?
DF: PTI’s panel-scale fan-out solution targets a broad range of applications, from IoT to advanced application processors for mobile devices. Our wafer-level fan-out solution has already met the requirements of high-performance mobile AP with fine L/S capability, and a similar concept is being adopted in our panel-scale production line.
YD: What are the key technical challenges for manufacturing fan-out on panel and how are you addressing them?
DF: Panel-scale fan-out involves several manufacturing processes, including chip placement on the carrier, molding, via revealing, RDL fabrication, and ball placement. In the early development stage we faced several challenges such as placement accuracy and warpage, which significantly affects the panel handling and processing. Warpage mitigation of the panels proved to be a major hurdle. To resolve the warping problem, we are closely collaborating with tools and materials suppliers for material selection and development of special process flows.
YD: What are the current features (line/space, number of RDL layers, pitch) for panel fan-out? What is your future target?
DF: The panel fan-out features are the same as those of the wafer form. Our current wafer-level fan-out offer is L/S 5/5 μm with 4 metal layers RDLs. Future challenges include finding a way to reduce to 3/3 and 2/2 μm.
YD: Do you think that fan-out on panel’s yield is sufficient enough to merit cost reduction per package as compared to wafer?
DF: The yield of fan-out on panel is expected to reach the same yield as that of wafer-level fan-out.
YD: What investment is required for a panel fan-out manufacturing line?
DF: Panel fan-out requires an estimated investment that’s 30% - 40% greater than WLP.
YD: There is no standardization of panel size and assembly process. In this scenario, how will the end-customer address the issue of multiple sourcing?
DF: The end-customer will accept the package if the performance, quality, and package outline meet their requirements. Both of our fan-out packages (wafer-level and panel-level) will satisfy these demands.
YD: Many players are working on advanced fan-out WLP technology with line/space features <5/5um. Do you think that these advanced features are also possible on panel fan-out?
DF: The line-space capability will be affected by the package design/structure, tools, and materials. Advanced features such as fine line/space have been developed for wafer-level fan-outs. The same features will be provided in our fan-out on panels.
YD: Do you think that in the future, panel fan-out will dominate fan-out packaging technology?
DF: Panel fan-out is only one available fan-out solution, and it will benefit large packages with multiple VLSI chip integration. Wafer-level fan out is applicable to more moderate package sizes. PTI will offer both solutions in order to suit our customers’ different application needs.
YD: What is PTI’s strategic focus roadmap for advanced packaging, and how does panel fan-out fit?
DF: PTI offers a variety of advanced packaging solutions (i.e. WLP, fan-out, 2.5D, and 3DIC) to satisfy various market demands. For high-performance applications like FPGA, CPU/GPU, and networking servers, PTI offers 2.5D and 3DIC solutions. For applications not requiring high I/O counts (PA, PMU, IC drivers, local power, RF transceivers, wireless connectivity, MEMS, and low-density memory), our WLP solutions are suitable.
Fan-out packages are available for applications requiring high I/O counts and multiple-chip integration, such as SoC + Memory, baseband, wireless modules, and wide I/O memory. Our panel-level fan-out will satisfy these demands, and it also offers a promising alternative to replace part of high-cost 2.5D and 3DIC.
YD: What can we expect in 2016 and 2017?
DF: We will install tools and setup processes for panel-level fan-out beginning Q3 2016. Qualification will be implemented in Q1 2017 and pilot production will commence Q2 2017. We have begun promoting fan-out on panels to potential customers, and we have received positive feedback. In the near future we expect more products to be installed with panel-level fan-out packages, and new product designs and qualifications will keep us exceedingly busy in 2017.
David Fang joined PTI in 1999 as Manager of Package Development. Since then, he has established packaging R&D capability and set up an R&D Lab, and held various positions in engineering and R&D. In 2015 he was promoted to CTO, heading up corporate R&D. Before joining PTI, David held managerial positions with several semiconductor companies. He has been granted 26 patents in Taiwan, the US, Japan, and China.
Sources: www.yole.fr / www.pti.com.tw
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