美光(Micron Technology, Inc.)6日發布新聞稿宣布，該公司已與三星電子(Samsung Electronics Co., Ltd.)攜手創立聯盟，將共同開發、推廣最新DRAM記憶體技術「Hybrid Memory Cube (混合記憶體立方體，簡稱HMC)」的開放式介面規格。
根據新聞稿，美光、三星是混合記憶體立方體聯盟(Hybrid Memory Cube Consortium，簡稱HMCC)的創始會員，將與開發夥伴Altera Corporation、Open Silicon, Inc.和Xilinx, Inc.密切合作，加速推出一系列相關技術。 HMCC一開始將著手定義技術規格，以便讓產品應用於大型網路、工業產品以及高效能運算等領域。
HMC可讓記憶體效能達到前所未有的水準，應用產品將包括網路、醫療、能源、無線通訊、運輸、安全監控等市場。舉例來說，整合可再生能源的智慧電網將可因HMC系統而變得更有效率、可靠且安全。
彭博社報導，美光記憶體行銷部總經理Scott Graham表示，相較於傳統的DRAM技術，HMC能以更低的能源傳輸更多資訊，預期可節省最多70%的能源。三星、美光錶示，目前市面上的DRAM是以並列的方式放置於小型電路板上，而隨著市場對記憶體、處理器運算速度的要求逐漸提高，傳統排列方式將出現瓶頸，且需要的電量、空間也太多。
英特爾技術長Justin Rattner曾在9月於科技論壇(IDF)中展示與美光合作開發的新款DRAM記憶體「Hybrid Memory Cube」，省電效率是現今DDR3的7倍，且能達到每秒傳送1兆位元的傳輸速度，未來將促使雲端運算伺服器、Ultrabook、電視、平板電腦及智慧型手機有大幅改進。
美光(Micron Technology, Inc.)6日發布新聞稿宣布，該公司已與三星電子(Samsung Electronics Co., Ltd.)攜手創立聯盟，將共同開發、推廣最新DRAM記憶體技術「Hybrid Memory Cube (混合記憶體立方體，簡稱HMC)」的開放式介面規格。
根據新聞稿，美光、三星是混合記憶體立方體聯盟(Hybrid Memory Cube Consortium，簡稱HMCC)的創始會員，將與開發夥伴Altera Corporation、Open Silicon, Inc.和Xilinx, Inc.密切合作，加速推出一系列相關技術。 HMCC一開始將著手定義技術規格，以便讓產品應用於大型網路、工業產品以及高效能運算等領域。
HMC可讓記憶體效能達到前所未有的水準，應用產品將包括網路、醫療、能源、無線通訊、運輸、安全監控等市場。舉例來說，整合可再生能源的智慧電網將可因HMC系統而變得更有效率、可靠且安全。
彭博社報導，美光記憶體行銷部總經理Scott Graham表示，相較於傳統的DRAM技術，HMC能以更低的能源傳輸更多資訊，預期可節省最多70%的能源。三星、美光錶示，目前市面上的DRAM是以並列的方式放置於小型電路板上，而隨著市場對記憶體、處理器運算速度的要求逐漸提高，傳統排列方式將出現瓶頸，且需要的電量、空間也太多。
英特爾技術長Justin Rattner曾在9月於科技論壇(IDF)中展示與美光合作開發的新款DRAM記憶體「Hybrid Memory Cube」，省電效率是現今DDR3的7倍，且能達到每秒傳送1兆位元的傳輸速度，未來將促使雲端運算伺服器、Ultrabook、電視、平板電腦及智慧型手機有大幅改進。
SAN FRANCISCO—Micron Technology Inc. and South Korea's Samsung Electronics Co. Ltd. Thursday (Oct. 6) announced the formation of an open consortium around hybrid memory cube (HMC), a technology that brings DRAM memory and logic processes together into one package to offer potential power efficiency, bandwidth, density and scalability advantages over traditional DRAM.
The goal of the Hybrid Memory Cube Consortium is to establish HMC as a new memory standard, according to Micron and Samsung. The consortium will begin meeting this month to develop a specification, which they expect to be released in 2012, the companies said.
The group plans to share an early draft of an HMC interface specification with OEMs, ASIC developers and other firms at an early point for review, discussion and development, according to Scott Graham, general manager of DRAM marketing at Micron. Graham said additional HMC Consortium members would be announced later this year.
"We fully expect that there will be additional developers comprised of OEMs and enablers who will essentially be guiding the development of this spec," Graham said.
HMC relies on through-silicon-vias (TSVs)for three-dimensional stacked layers of memory with interconnect that increases performance and lowers power consumption. It also incorporates a logic layer that allows for multiple configurations for scalable bandwidth and the design flexibility for HMC to be implemented on multiple platforms, across many applications, according to Micron and Samsung. The technology also promises wide, high-speed local buses for data movement, advanced memory controller functions, DRAM control at memory, reduced memory controller complexity and increased efficiency, according to the companies.
In February, Micron introduced HMC's ability to integrate DRAM and logic processes together in one package. The current HMC platform—demonstrated last month—has validated that it can run at 128 FB/s, providing significant bandwidth, density and energy efficiency improvements, according to Micron.
Micron and Samsung believe that HMC has the potential to deliver significant improvements for applications ranging from networking and data center to consumer products such as media tablets and cards. HMC also represents a fundamental shift from current memory architectures, and driving its integration and adoption as an open standard will be a major undertaking, the companies said.
Graham said the companies believe that HMC will have the greatest near-term impact in areas where performance and energy efficiency are most critical, such as networking and high-performance computing. But ultimately the companies believe the technology will be adopted into a wide-variety of wireless, medical, energy, transportation and security devices, he said.
Graham described HMC as a response to significant challenges facing traditional DRAM, including the so-called "memory wall" created by the inability of DRAM vendors to march the performance improvements of processors. As a result, memory has become a significant bottleneck for system performance, he said.
"The CPUs are capable of processing a lot more information than the DRAM is able to deliver," said Pablo Temprano, director of DRAM marketing at Samsung Semiconductor.
In response to the disparity between the speed of processors and memory, engineers introduced a hierarchy of cache memory that is capable of running at processor clock speeds, according to Graham. But with the advent of multi-core, multi-threaded processors, the memory needs of computational algorithms sometimes exceed the capacity of the processor cache, he said.
HMC offers the potential to alleviate this bottleneck, according to Graham and Temprano. A single HMC unit can provide more than 15 times the bandwidth of a DDR3 module and offer significant improvement in response to a random request stream, reducing system latency, they said.
資料來源:http://www.eetimes.com/electronics-news/4229220/Micron--Samsung-seek-hybrid-memory-spec-
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