真乄科技業的頂尖投資團隊

Global semiconductor chip manufacturing trends are steadily moving towards producing chips of smaller and smaller total silicon area, while at the same time introducing an increasing number of interconnects per chip. These opposing trends result in the need for interconnect pitch reductions and the need for placing bonding pads at the chip/package interface. Since the shrinking of features on the silicon-side is progressing at a faster rate than on the circuit board-side, noticeable limitations are occurring at the package level. To alleviate this interconnect gap, traditional technologies, such as FC-CSP or WB/FC-BGA, are incorporating additional substrates to re-route interconnect wires and accommodate increased interconnect densities; however, this comes with an associated increased package cost with the increase in the number of I/Os. Fan-in WLCSP, another packaging platform, although using a substrate-less approach, also faces inherent limitations due to the die area available for re-routing.

Fan-out wafer-level packaging (FOWLP) seems best able to address the most stringent requirements for integrating advanced chips, and, for this reason, has become one of the most promising solutions for packaging semiconductor devices. FOWLP provides a platform that enables integration of advanced devices with increasingly greater numbers of I/Os into smaller packages, with improved electrical and thermal performance as an added benefit. The fan-out platform is based on a molding infrastructure, where small dies are embedded into a carrier that becomes a kind of reconstituted wafer, allowing interconnects to be re-routed to the outside of the dies, thus reducing the amount of silicon real estate needed to accommodate high numbers of I/Os.

"FOWLP has significant potential to reduce costs as it scales to volume production, since it eliminates the need for substrates--the major cost component in today’s laminate packages—simplifying supply chain logistics and reducing the costs associated with carrying substrate inventory. Equally important, fan-out is also a scalable platform technology, with a roadmap for further cost reduction, along with a roadmap for supporting the integration of future generation devices.  While mature BGA packaging technology has little room left to further wring out costs, fan-out has plenty of room to grow, both by scaling up in volume and by scaling up beyond 300mm wafers, first to panels, and then to larger and larger panels as yields improve. Another significant benefit of the fan-out approach is extendibility to even higher density I/Os and multiple chip packages, and package-on-package solutions, since FOWLP is not limited by the need to fit all the connections under the chip," explains Rozalia Beica from Yole Développement.

Investments in equipment and other necessary infrastructure to support fan-out technology have already been successfully made, and devices using fan-out technology are being produced today with high yields in high volume manufacturing at major OSATs. Due to its successful manufacturing implementation, combined with several key benefits, and with the added flexibility such a packaging approach can bring, adoption of fan-out wafer-level packaging is expected to grow even further.

Yole Développement recently had the opportunity to interview Dr. Raj Pendse, Vice President and Chief Marketing Officer of STATS ChipPAC, and Steffen Kröhnert, Director of Technology, Technical Marketing of NANIUM. They share their points of view on embedded Wafer-Level Ball Grid Array (eWLB) / fan-out wafer-level packaging platform with us, as follows.

Yole Développement: Could you please describe the challenges existing today with traditional packaging technologies?

Raj Pendse: Traditional packaging technologies lack the scalability to cost-effectively fulfill the rapidly increasing functional requirements of higher I/O density, higher bandwidths, and low power consumption in smaller package sizes. As opposed to over-extending the density and design rules of traditional package substrates beyond their natural sweet spot to meet the increasing requirements, which can be unduly costly, customers can adopt the FOWLP approach. FOWLP provides the necessary jump and head room in density and form factor while being cost competitive with incumbent packaging options.

Steffen Kröhnert: Besides providing the basic functions of interconnection and mechanical protection of the dies, electronics packaging always impacts system performance, both electrically and thermally. Currently, regardless of the different and varying dimensions, the number of layers and interfaces, the type of construction, and even with the additional implementation of available heat dissipation options, traditional packaging technologies are reaching their limits. Indeed, the most common methods for packaging, assembly and interconnect, such as Fan-In WLP/ WLCSP, metal lead frame-based, or organic laminate IC substrate-based, FCBGA, and wire bond BGA/ LGA often do not fulfill the requirements of leading-edge systems anymore, as the routing and bumping demands these traditional technologies attempt to service is no longer in line with today’s needs and available chip size areas.

Today’s main driver for advanced packaging is the mobile communication consumer market, which aims to reduce – or even turn into an advantage for system performance - the impact coming from the package. No packaging technology other than Fan-Out WLP/ eWLB allows for the fulfillment of such high flexibility and integration density demands at a reasonable cost.

YD: From your point of view, why does the industry need eWLB? What are the advantages (cost, performance, integration, etc.) that eWLB can bring versus current technologies?

RP: There are a number of industry requirements where eWLB provides clear advantages to customers.  The most notable are:

- The increasing I/O density of new Si nodes requires a commensurate increase in routing density at the package level. Being based on a thin film process, eWLB provides a 1.5-2X increase in routing density (measured in terms of lines/spaces and vias) compared with traditional packaging technologies, which are typically based on laminate substrates.

- To fulfill the needs of mobile/handheld products and new wearable devices, packages need to become progressively smaller and thinner. Again, the thin film backbone of the eWLB package enables unparalleled reductions in package size and thickness which is not attainable with traditional substrate-based packages.

- As electrical noise margins continuously shrink to achieve higher electrical performance, there is a need for the parasitics induced by the package to be reduced. Smaller, thinner and more controllable circuit features (notably, thinner dielectric materials) in eWLB technology enables a reduction in parasitic effects induced by the package.

- The decreasing yields with increasing die sizes for new Si nodes make it economical to split (or partition) the Si into smaller die and re-integrate them on a separate substrate, an approach known as Si partitioning and re-integration (often referred to as 2.5D integration). This approach requires very fine features at the substrate level which are made possible with eWLB technology.

 
Examples of eWLB packages (Courtesy of STATS ChipPAC)

SK: The industry’s demands will naturally require the introduction of fan-out embedding technologies like eWLB, given the main drivers of performance, form-factor and cost. eWLB is the available technology that effectively addresses all these drivers. When it comes to performance, eWLB’s architecture, based on short interconnection lengths, widths, and thicknesses, offers excellent electrical performance, generating lower package-parasitics impacts than traditional technologies. Form-factor wise, eWLB allows for higher integration density, and currently is the smallest system footprint and thinnest commercially available package solution in HVM. No other packaging technology allows such high flexibility and integration density, with die-to-die, die-to-passives, and passives-to-passives placement distances below 100um. This grants the possibility of making unprecedentedly short connections between the functional elements.

When it comes to cost, eWLB is scalable and can be produced on large wafer and panel sizes. The batch processes that mainly comprise its production flow are highly efficient, handling thousands of packages in parallel at the same time, and thereby reducing the costs of the technology.

eWLB is still setting in, but is nonetheless already the best option for high speed and RF applications. The increasing penetration of eWLB into new markets and applications will increase eWLB production volumes, which will lead to an attractive cost reduction roadmap towards this technology’s “sweet spot”. Traditional packaging technologies, on the other hand, have already entered saturation level and currently offer very little cost-reduction opportunities.

YD: Could you talk more about infrastructure readiness, and also about future support of this technology for even more advanced packages?

RP: We are at a watershed moment today with FOWLP. The manufacturing process is well established and customer adoption is rapidly increasing for a wide range of applications. As we continue to introduce new FOWLP designs, we are also driving important optimizations in the manufacturing infrastructure, resulting in even better value for our customers.

eWLB technology leverages the well-established infrastructure for Si wafer fabrication today,  providing an expedient path for manufacturing. Increased customer adoption has brought more suppliers into the mix, making the technology more prevalent, with multiple sources available. This has also triggered interest among the leading equipment manufacturers to participate in the associated equipment business.

That being said, there is ample room for further optimization of the manufacturing infrastructure for significantly better capital intensity and a lower unit cost by finding approaches that match the specific process requirements of eWLB technology versus the characteristics of standard Si wafer fabrication. For example, the design rules required for eWLB are much coarser than the sub-micron or nano-scale feature sizes of Si wafer fabrication, making that equipment “overkill” for eWLB manufacturing, and this provides an area of opportunity for optimization. eWLB manufacturing lends itself to the use of significantly larger carriers, which has a direct impact on capital intensity and cost, but is not applicable to Si wafer fabrication. Similarly, the manufacturing process can be tailored and optimized more for FOWLP technology, which becomes viable as the adoption rate increases.

SK: Even though it is regarded as a technology that is only just now breaking out, the truth is that the entire infrastructure needed for eWLB production already exists, and is installed and in place. This is another example of how traditional back-end packaging, assembly and interconnect processes are moving towards the mid-end, that is, towards wafer post-processing, allowing them to benefit from existing, continuously developed  front-end wafer fab processing equipment.

Moreover, it is estimated that more than 1.5 billion eWLB products have been shipped into the market in the last 6-7 years, which means that eWLB technology can actually be considered mature. Unlike other mature technologies, however, eWLB technology platform development is still ongoing, continuously opening the platform for new application needs, enhancing its potential to adapt. This is an attribute that particularly distinguishes eWLB, making it a very promising technology for future packaging trends as well. We are just at the beginning.

As an example, improvement in eWLB materials led just recently to significantly increased package reliability and robustness. This, in turn, added value to the technology, which became appealing even for automotive applications, a field where Wafer-Level Chip Size Packaging is still not well established and positioned. And, last but not least, very interesting cost saving potentials are reflected in the eWLB cost reduction roadmap, enabled by optimized and more efficient manufacturing processes, new materials, improved material utilization and reduced material cost able to be realized with increasing volumes of product.

YD: What are the applications and packaging complexity addressed by eWLB?

RP: eWLB has been particularly successful in mobile applications, with the largest demand in baseband processors, RF transceivers and power management ICs.  We are now seeing a wider adoption in application processors, network/telecom hardware, and, most recently, in MEMS and modules. These latter applications are made possible by the ability to produce larger body sizes at high yields and the ability to uniquely “marry” eWLB technology with other “adjacent” technologies, like flip chip and wire bond,  to provide the optimum solution.

eWLB technology in a PoP configuration has received  considerable customer interest for advanced Application Processor packaging by virtue of the higher routing density and breakthrough form factors that are unattainable with traditional packaging approaches.

 
eWLB Package-on-Package (eWLB-PoP) (Courtesy of STATS ChipPAC)

eWLB has also found success in 2.5D and 3D integration (including Si partitioning) as a more cost effective and infrastructure-friendly alternative to TSVs. eWLB technology achieves tighter line/spaces for a range of 2.5D and 3D configurations that deliver product advantages to customers in terms of higher performance, higher frequencies, higher bandwidth and thinner package profiles.

 The 3D eWLB configuration is accomplished by means of a unique face-to-face bonding approach (which we also refer to as the “marsupial configuration”) which obviates the more expensive TSV interconnection while achieving high bandwidth 3D integration.

SK: One of the major advances brought forward by the eWLB technology is its astounding integration capability. We see the trend that large System-on-Chip (SoC) dies are split in several smaller dies for economic reasons. “More-than-Moore”, the heterogeneous integration of different active and passive elements, embedded very close to each other in the package, is used to connect them again, targeting “SoC-like” performance. System-in-Package (SiP) is a growing trend for improved system performance, system form-factor reduction, and last but not least, also for system cost reduction. Thus far, Fan-Out WLP/ eWLB is the best available answer to all of these challenges. eWLB allows system integration on the wafer-level (WLSiP) with the highest integration density known in the electronics packaging world, and offers answers to problems other technologies have encountered. For instance, eWLB provides a smaller footprint and a thinner package than FCBGA (there is no need to underfill eWLB on PCB); it does not demand restrictions for ball pitch, thus covering the I/O gap between IC and PCB; and it offers better board-level reliability, bare die backside protection and thermal performance  compared to classic Fan-In WLP/ WLCSP.

Recon-Wafer with 5x5mm² Die in 8x8mm² eWLB Package running in HVM (Courtesy of NANIUM)

Additionally, eWLB technology offers very high product reliability, both due to its excellent performance and to the possibility of testing eWLB integrated solutions at a reconstituted wafer-level. The latter encompasses no risk of dicing-related fails, as chip dicing is done prior to reconstituted wafer test. eWLB’s unprecedented  quality and flexibility in integration has been driving complexity away from single die, single RDL-Layer fan-out only. There are other attractive WLSiP (System-in-Package on Wafer-Level), eWLB-based PoP (Package-on-Package), side-by-side Multi-Chip (MCP) and stacked die solutions including 3D IC integration face-to-face (F2F) chip assembly on eWLB base packages. These, in turn, will be the key to ensuring excellent system performance and for allowing a wide range of functionalities at a reduced footprint and package height.

YD: Why is eWLB better than alternative technologies now being developed or better than alternative technologies now at an early stage?

RP: The notable technologies being developed or at an early stage in the industry can be broadly sub-divided into two groups - high density organic substrates (which are based on an extension of traditional packaging) and TSVs (which are based on Si wafer fabrication). It is fair to say that the former group is not extendible to the densities required for next generation devices while the latter is largely an overkill, too aggressive for what is needed and, therefore, unduly expensive.

FOWLP provides the optimum technology platform in terms of density and cost as it combines the best of both worlds – thin film processing from the Si world to achieve the ultimate in density and thin profile, with back-end operations such as compression molding and large carrier processing from the packaging world that together provide the most cost effective packaging solution.

SK:  eWLB is a substrate-less technology, as routing is realized via thin-film processes directly on the chip and epoxy mold compound; eWLB does not require underfill when assembled to PCB, and, due to the standard BGA pitch, allows for the possibility for devices to be mounted to standard PCBs instead of the High Density Interconnect (HDI) PCBs like FlipChip BGA (FCBGA) substrates. The allocation of die(s) and passives is accomplished using the fan-out zone as an additional routing space. The active and passive dies and components are embedded in the interposer itself, which allows us to regard eWLB as an “Active Interposer” technology.

Of course, there are other “Active Interposer” solutions available that embed active and passive elements, e.g. into organic laminated IC-Substrates and PCBs. An example of this is the ECP® (Embedded Component Packaging), by the Austrian company AT&S. NANIUM considers ECP® as a complementary embedding technology to eWLB and works together with AT&S, offering an efficient supply chain solution for the customers of both companies.

Each packaging technology has its “sweet spot” in terms of package size and thickness, integration capability, routing traces line/ space width, I/O count, component and board-level reliability, mechanical robustness, heat dissipation capabilities, and cost. Therefore, it is important to understand the requirements of different applications and to offer to the customer the solution, serving those requirements best.

The simplified supply chain and manufacturing infrastructure eWLB offers, and its RoHS and REACH compliancy, are only two of the many other reasons to justify eWLB.

Fan-Out WLP Technology eWLB – An active interposer (Courtesy of NANIUM)

YD: Are there any challenges perceived by the industry with eWLB? If yes, would you please address them, highlighting advantages for eWLB in the face of these challenges?

RP: The primary challenges perceived by the industry are in the areas of supply assurance (multi sourcing) and cost. The former is being addressed with the rapid entry of multiple OSATs and Foundries into fan-out wafer level manufacturing.  As for cost, it is a function of the IC design and the density of the next (downstream) tier of packaging (the mother board).  According to our estimates, eWLB already provides the lowest cost solution for approximately 30% of designs in the mobile space today and that number is estimated to go to > 80% with large carrier manufacturing.  As FOWLP adoption proliferates across the full application space that can be addressed by this technology, and the progressive reduction of cost in the process occurs, the sweet spot for FOWLP will continue to expand. 

SK:  Future demand for eWLB will not be an issue. In addition to applications in the mobile communication consumer market, other commercial applications will increasingly have the same demands for miniaturization and for reductions in footprint, thickness and weight that mobile consumer had. And these other commercial applications will find the same answer, eWLB, just like mobile consumer did. The biggest challenge to be faced by eWLB could be the industry’s mindset, which might need to change for eWLB to attain production efficiency. Moving system integration from board-level into package-level is one answer. However, in order to successfully optimize performance and cost, one has to consider the whole system. This still requires some changes in mindset and established practices in the industry, including, noticeably, changes in the available EDA tools, in the current ability to run Chip-Package-Board Co-Design, and even in organizational setups and structures.

YD: Thank you Raj and Steffen for your thoughtful answers to our questions.

If Intel and the mobile sector have led the adoption of fan-out wafer-level packaging technology so far, driven by the need for thinner packages and lower costs, other segments, such as the industrial, automotive, and medical markets, are also expected to increasingly start adopting this packaging platform as the infrastructure matures. Yole Développement forecasts the use of fan-out technology to start ramping up sharply in 2015, projecting the fan-out market to average ~32% compound annual growth, reaching ~$640 million by 2020. Stay tuned for more information on eWLB... Updates of market and technology trends will be soon released as part of the new, 2014  “Embedded Die and Fan-Out Business Report”.

Source:http://www.nanium.com/