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Yole Développement's report Status of the Advanced Packaging Industry 2015 

Yole Développement (Yole) has analyzed three dimensional through-silicon via (3D TSV) integration for more than 10 years, ever since a microphone from SonionMems first used TSVs in MEMS devices, and Toshiba adopted TSVs in image sensors. Then the first signs of TSV adoption in memory integration came from multiple developments at Samsung, Micron and Toshiba. Meanwhile, Qualcomm, ST Ericsson and other application processor designers were interested in 3D integration of memory and logic die.

Today, TSVs have been widely adopted by MEMS and CMOS image sensor manufacturers, driven by the need to further shrink form factors and ease package integration. Key memory players are also entering mass production, driven by the need for higher bandwidth performance. Very recently, the second generation of High Bandwidth Memory (HBM2) interface has entered mass production at Samsung. For more details on 3D TSV integration, see Yole’s report 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Business Update.

The name HBM2 is justified. Samsung’s new DRAM package features 256Gbps of bandwidth, doubling the current HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36Gbps bandwidth of a 4Gb GDDR5 DRAM chip, which at 9Gbps has the fastest data speed per pin among currently manufactured DRAM chips. Samsung’s 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb-GDDR5-based solution, and embeds error-correcting code functionality to offer high reliability.

In addition, Samsung plans to produce an 8GB HBM2 DRAM package within 2016. By specifying 8GB HBM2 DRAM in graphics cards, designers will be able to profit from space savings of more than 95 percent compared to using GDDR5 DRAM. This enables better solutions for compact devices that require high-level graphics computing capabilities.

The company will steadily increase production volume of its HBM2 DRAM over the remainder of the year to meet anticipated growth in market demand for network systems and servers.

The applications targeted are high-end, like high performance computing (HPC), advanced graphics and network systems, as well as enterprise servers. However, this second generation at Samsung paves the way for wider adoption of 3D TSV stacked memories in lower-end applications in the next 3 years. As volumes go up and price goes down, we can expect more announcements from Samsung and its main competitors.

IoT driven semiconductor industry consolidation is reflecting into a highly dynamic Advanced Packaging landscape. Demand for advanced packaging and market size is increasing.
Focus is turning to integration and wafer level packages to enable a functionality driven roadmap and revive the cost/performance curve

A transformation of the semiconductor industry is under way – advanced packaging is part of the scaling and functionality roadmaps
The latest events in the technology market indicate that 2015 marks the beginning of an exciting new era for the IT and electronics industry. At semiconductor supply chain level, the industry entered a profound consolidation phase with high M&A activity reshaping the business landscape. Front-End-of-Line device scaling and related cost reduction are deviating from the path they followed for the past few decades, with Moore’s law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. As the smartphone market matures, new forces are appearing in the form of the Internet of Things (IoT). While the mobile sector continues to drive the market, the scent of IoT is already spreading in the consumer sector with products such as wearables and first smart home appliances. IoT market, application and technology segmentation has begun. Companies across the industry are restructuring, merging and acquiring in order to adjust their portfolio, enable a complete platform offer and establish leading positions on the market.

At the level of technology, as profitability of FEOL scaling options remains uncertain and IoT promises application diversification, the spotlight is now turning to advanced packages for:

• Cost reduction
• Performance boost
• Functional integration

In order to answer market demands, the advanced packaging segment focuses on integration and wafer level packages (WLP). Emerging packages such as Fan-Out WLP, 2.5D/3D IC and related System-in-Package solutions aim to bridge the gap and revive the cost/performance curve.

How will the advanced packaging industry evolve, which changes in the semiconductor supply chain are taking place and which packaging technologies will be most critical in the years to come? In this report, Yole Developpement (Yole) brings a thorough analysis of the advanced packaging industry and its future development covering platforms Fan-Out WLP, Fan-In WLP, Flip Chip and 2.5D / 3D.

Advanced Packaging will reach 44% of packaging services and a revenue of $30B by 2020

According to Yole Développement estimates, advanced packaging services revenue will increase by  $9.8B from 2014 to 2020 at a CAGR of 7%, in majority due to high volume adoption of Fan-Out WLP, 2.5D / 3D and evolution and growth of Fan-In WLP and Flip-Chip. Advanced packages currently account for 38% of all packaging services or $20.2B and are expected to grow share to 44% and $30B by 2020.

The mobile sector remains the main advanced packaging market with smartphones and tablets as end products. Other high volume applications include servers, PC, game stations, HDD/USB, WiFi hardware, base stations, TVs and set top boxes. The scent of IoT is spreading with first products already on the market in the form of wearables and smart home appliances. Further early stage investments are made in sectors such as smart cities, connected cars, various industrial devices and medical applications.

The Flip-Chip platform represents a large mature market and leads in packaging services revenue and wafer count.  Fan-In WLP leads in unit count due to small size compared to demanded volume. Adoption of wafer level packages continues. Teardowns performed by Yole and its sister company, System Plus Consulting on 3 high end smartphones (iPhone 6+, Samsung Galaxy S6 and Huawei Ascend Mate 7) indicated a high penetration rate of WLP, 30% on average. Fan-Out WLP is expected to make a major breakthrough within the next year, likely led by TSMC inFO PoP and followed by other Fan-Out multi die solutions. Long term, a bright future lies ahead for wafer level packages with respect to IoT requirements as they are well position to answer related cost, form and functional integration demands. When it comes to advanced feature sizes, a competitive sub 10 µm / 10 µm arena is established where organic wafer level packages aggressively compete with advanced organic Flip-Chip substrates and 2.5D / 3D Si/glass interposers.

As WLP pin counts grow, thicknesses and overall cost decrease, the evolution of Fan-In WLP and in particular a breakthrough of Fan-Out WLP are expected to result in a takeover of a part of the Flip Chip market. With the breakthrough of Fan-Out WLP, the packaging landscape might drastically change, with an IDM and foundry leading all packaging services by wafer count.

A full analysis is available in the report including revenue, wafer and unit forecasts per advanced packaging platform and production breakdown by device type such as analog/mixed signal, wireless/RF, logic and memory, CMOS image sensors, MEMS, LED and LCD display drivers.
 

Advanced Packaging supply chain – the end of OSATs as we know today?  
The semiconductor industry worth $335B in annual revenue is the spine of the mobile sector and is now transforming itself to be the hardware enabler of the IoT age.  Due to cost pressures and portfolio completion, high M&A activity is in progress with record breaking deals and a whopping $120B already spent in 2015 alone - more than the last 10 years combined! How is the semiconductor business landscape and in particular advanced packaging landscape changing, who are the leaders, what is their activity by packaging platform and are IDMs and foundries taking over advanced packaging? Get the thorough analysis in this report!

Furthermore, this report brings a financial analysis with insight into gross margins, R&D expenses, net incomes and related industry segmentation. Advanced packages are also segmented by package features such as pin count, pitch, thickness, footprint, price with included analysis of their feature trends. A specialized section is dedicated to the breakthrough of Fan-Out WLP with revenue, wafer and unit forecasts until 2020 and high volume adoption of the 2.5 / 3D platform.

The advanced packaging industry is facing complex market and technology transformations, but is propelled by strong drivers perpetually increasing demand. With advanced packaging platforms still building on the smartphone market and new IoT driven applications on the horizon, leftover capacity in 2014 is forecasted to be exceeded by 6 times by 2020!  Regarding wafer size, majority of advanced packages are still processed on 200 mm wafers, however, if total wafer surface is taken into account, processing on 300 mm wafers is dominant.

For more information see the article: Samsung begins mass producing world’s fastest DRAM – Based on newest high mandwidth memory (HBM) interface

Author: Jean-Christophe Eloy, President and CEO at Yole Développement

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